A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.

A method for controlling functional elements and a device for use in bioprocess engineering or medical technology is disclosed. The method includes providing a first functional element, which has a memory, in which items of element information having specifications about the type and the function of the functional element are stored, and providing a second functional element. The method includes connecting the first and the second functional element to a control unit, reading the items of element information out of the first functional element and carrying out a check of the read-out items of element information from the second functional element or using items of information which are stored in the control unit. The first functional element is controlled by the control unit in dependence on the check or in dependence on the items of element information.

Disclosed is a method of operating a storage device which includes a non-volatile memory device. The method includes informing a host that a designation functionality for designating a data criticality and a priority to namespaces of the non-volatile memory device is possible, enabling the designation functionality in response to receiving an approval of the designation functionality, receiving, from the host, a first request for designating a data criticality and a priority for a first namespace of the namespaces, and generating a namespace mapping table in response to the first request.

A memory chip comprises a first memory controller, a first data storage zone, a security unit and an address configuration unit. The first data storage zone is coupled to the first memory controller, and represented by a first physical address range. The security unit is coupled to the first memory controller. The address configuration unit is coupled to the first memory controller. The memory chip is configured to be coupled between a host controller and another memory chip. The another memory chip comprises a second data storage zone represented by a second physical address range. The address configuration unit records one or more relationships of a logical address range corresponding to the first physical address range and the second physical address range. The security unit is configured to encrypt and decrypt data in the first data storage zone and the second data storage zone.

A data storage device includes a nonvolatile memory including a plurality of memory blocks and page buffers for data input/output, the page buffers being electrically connected to the plurality of memory blocks, respectively, and a controller configured to, when a number of free memory blocks among the plurality of memory blocks is equal to or less than a predetermined threshold number, select, as a candidate source memory block group, memory blocks each having a number of valid pages equal to or less than a predetermined number within the nonvolatile memory, select, as a source memory block, a memory block having a minimum amount of time required to read valid data from the valid page within the candidate source memory block group and perform a garbage collection operation to the source memory block.

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison.

Disclosed herein is a computer-implemented method for storing Merkle tree data in memory. The Merkle tree data comprising uncle node data, first nephew node data and second nephew node data. The computer implemented method comprises determining a first nephew node memory address, determining a second nephew node memory address, storing the uncle node data at the uncle node memory address, storing the first nephew node data at the first nephew node memory address, and storing the second nephew node data at the second nephew node memory address. The first nephew node memory address is less than the uncle node memory address and the second nephew node memory address is greater than the uncle node memory address, or the first nephew node memory address is greater than the uncle node memory address and the second nephew node memory address is less than the uncle node memory address.

A solid state drive having a drive aggregator and a plurality of component solid state drive, including a first component solid state drive and a second component solid state drive. The drive aggregator has at least one host interface, and a plurality of drive interfaces connected to the plurality of component solid state drives. The drive aggregator is configured to generate, in the second solid state drive, a copy of a dataset that is stored in the first component solid state drive. In response to a failure of the first component solid state drive, the drive aggregator is configured to substitute a function of the first component solid state drive with respect to the dataset with a corresponding function of the second component solid state drive, based on the copy of the dataset generated in the second component solid state drive.

A method, computer program product, and computer system for identifying, by a computing device, a list of objects containing a plurality of physical layer blocks (PLBs). One or more next PLBs of the plurality of PLBs may be allocated from a selected free object of the list of objects. One or more additional free objects from the list of objects may be generated. Garbage collection may be performed between an inactive object of the plurality of objects and the selected free object.

A memory system includes a first memory device including a plurality of first physical blocks; a second memory device including a plurality of second physical blocks; a first core suitable for managing a plurality of first super blocks that store data associated with a first logical address, the plurality of first super blocks being mapped to the plurality of first physical blocks; a second core suitable for managing a plurality of second super blocks that store data associated with a second logical address, the plurality of second super blocks being mapped to the plurality of second physical blocks; a global wear-leveling manager suitable for changing mapping between the first physical blocks, which are mapped to one among the first super blocks, and the second physical blocks, which are mapped to one among the second super blocks based on degrees of wear of the first and second super blocks.