A memory controller may be configured with command logic that is capable of sending a memory access command having incomplete address information via a command/address bus that connects the memory controller to memory modules. The memory controller may send the memory access command via the bus for accessing data stored at memory locations of the memory modules. The memory locations may correspond to different near-memory generated reflecting that the data is not address aligned across the memory modules. Nonetheless, because of the near-memory address generation, the memory controller can send the memory access command having incomplete address information for accessing the data stored at the different addresses, as opposed to having to send multiple memory access commands specifying complete address information on the bus for accessing the data at the different addresses, thereby conserving usage of the available bus bandwidth, reducing power consumption, and increasing compute throughput.

A memory apparatus and a method for processing data the same are suggested to process 10-bit or 12-bit data. A processor that uses 10-bit or 12-bit data can efficiently store 10-bit or 12-bit data and provide a flexible memory access method that reduces memory usage. To this end, by adding a new memory bank that is ¼ of the size of an existing memory bank word, when storing data in 10-bit units, 2 out of 10 bits can be stored in a new memory bank to reduce memory waste. In addition, when 8-bit data is stored using a flexible memory structure, data can be stored in the same way as a previously operated memory bank.

A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

According to one embodiment, when receiving a write command including a first identifier of identifiers for accessing regions from a host, a memory system allocates one block of a common free block group shared by the regions as a write destination block for the region corresponding to the first identifier. When receiving a copy command including a block address of a copy source block of blocks belonging to the region corresponding to the first identifier, and an identifier of a copy destination target region indicative of the first identifier from the host, the memory system allocates one block as a copy destination block for the region corresponding to the first identifier, and copies data from the copy source block to the copy destination block.

A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.

A computing device divides an area of a main memory wherein a data structure is saved into NbS1 subdivisions, and then the computing device computes a weight w.sub.S,NbS1(k) for each of the NbS1 subdivisions using the following relationship: w.sub.S,NbS1(k)=P.sub.S(1+(k−1)×(NbS0−1)/(NbS1−1)), where: k is the order number k of one of the NbS1 subdivisions, and P.sub.S( ) is a predetermined function that is continuous over an interval [1; NbS0] and defined over each interval [k.sub.0, k.sub.0+1] by a polynomial of order less than four, where k.sub.0 is an integer order number contained in the interval [1; NbS0], and then when a datum D.sub.k,n contained in a subdivision k of the main memory has to be transferred to a secondary memory, the computing device transfers a block of w.sub.S,NbS1(k) data containing the datum D.sub.k,n where w.sub.S,NbS1(k) is the weight computed for this subdivision k.

In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to dynamically cause the first communication line to communicate a clock signal to a first device group including one or more first devices to couple to the interconnect and dynamically cause the second communication line to communicate a data signal to the first device group when a communication is to be addressed to at least one of the one or more first devices of the first device group, such that the communication is transparent to at least another device group to couple to the interconnect. Other embodiments are described and claimed.

A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

A device is provided that includes a first memory and a second memory and an accessing circuit. Actual addresses of the first memory and the second memory alternately correspond to reference addresses of a processing circuit. The accessing circuit is configured to perform the steps outlined below. A read command corresponding to a reference read address is received from the processing circuit to convert the reference read address to an actual read address of the first memory and the second memory. A first read data is read from a first one of the first memory and the second memory according to the actual read address and a second read data is prefetched from a second one of the first memory and a second memory according to a next first read address simultaneously.