Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.

A memory apparatus and a method for processing data the same are suggested to process 10-bit or 12-bit data. A processor that uses 10-bit or 12-bit data can efficiently store 10-bit or 12-bit data and provide a flexible memory access method that reduces memory usage. To this end, by adding a new memory bank that is of the size of an existing memory bank word, when storing data in 10-bit units, 2 out of 10 bits can be stored in a new memory bank to reduce memory waste. In addition, when 8-bit data is stored using a flexible memory structure, data can be stored in the same way as a previously operated memory bank.

A cache memory includes a first cache area corresponding to even addresses, and a second cache area corresponding to odd addresses, wherein each of the first and second cache areas includes a plurality of cache sets, and each cache set includes a data set field suitable for storing data corresponding to an address among the even and odd addresses, and a pair field suitable for storing information on a location where data corresponding to an adjacent address which is adjacent to an address corresponding to the stored data is stored.

A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.

An unbalanced plane management method, an associated data storage device and the controller thereof are provided. The unbalanced plane management method may include: setting an unbalanced plane number; selecting at least one plane with a plane count calculated by subtracting the unbalanced plane number from a maximum plane number, and recording at least one set of blocks of the at least one plane to a block skip table; according to block numbers as indexes, combining blocks of unselected planes into super blocks, wherein said super blocks respectively correspond to said block numbers; and recording total capacity of all super blocks and the unbalanced plane number, to generate a latest record of records of multiple types of storage capacity, for further setting storage capacity configuration of the data storage device, wherein said all super blocks include said super blocks.

Systems and methods for writing data are provided. A lock-free container and methods of writing to the lock-free container are disclosed. The container is associated with a tail pointer that identifies free space in the container. Threads writing to the container access the tail pointer and update an offset in the tail pointer to account for a size of a write to the container. Multiple threads can write to the same container without having to contend for a container lock.

An intelligent tile-based memory bandwidth management solution executed by an address aperture, such as a compression address aperture, services linearly addressed data requests (read requests and write requests) from a processor to data stored in a memory component having a tile-based address structure. For read requests, the aperture stores previously read tiles (full or partial) in a tile-aware cache and then seeks to service future read requests from the cache instead of the long-term memory component. For write requests, the aperture stores the write data in the tile-aware cache and assembles the data with write data from other write requests so that full tile data writes to the long-term memory may be achieved in lieu of excessive partial-tile writes.

According to one embodiment, when receiving a write command including a first identifier of identifiers for accessing regions from a host, a memory system allocates one block of a common free block group shared by the regions as a write destination block for the region corresponding to the first identifier. When receiving a copy command including a block address of a copy source block of blocks belonging to the region corresponding to the first identifier, and an identifier of a copy destination target region indicative of the first identifier from the host, the memory system allocates one block as a copy destination block for the region corresponding to the first identifier, and copies data from the copy source block to the copy destination block.

Provided are a mode conversion method and a mode conversion apparatus for a nonvolatile memory. The method includes: receiving a first user command that is sent by an upper computer and belongs to a user mode, where the first user command includes an invoking path disabling instruction; sending an enable signal according to the invoking path disabling instruction; and disabling the module path for controlling the high-bit I/O ports [15:8] in the X16 nonvolatile memory according to the enable signal. After the module path for controlling the high-bit I/O ports [15:8] in the nonvolatile memory is disabled, data transmission and reception of the nonvolatile memory are implemented through the low-bit I/O ports [7:0], and the X16 nonvolatile memory is converted into an X8 mode.