Patent classifications
G06F12/0692
TECHNIQUES FOR EFFICIENTLY PARTITIONING MEMORY
Techniques are disclosed for allocating a global memory space defined within physical memory devices into strided memory space(s) (SMS) and partition memory space(s) (PMS). In an embodiment, a SMS is mapped across all of the devices, and a PMS is mapped to a subset of the devices to ensure resource isolation between separate PMSs. Typically, a memory space is allocated in unit sizes. When the locations mapped to most of the SMS align to an integer number of the unit size, a common boundary can be formed between the SMS and the one or more PMSs in each of the devices. Such a boundary can advantageously minimize a region of locations that are not available for allocation in the global memory spaces. In an embodiment, when a strided allocation is not an integer number of the unit size, a remainder is mapped to locations for one or more PMSs.
Apparatus, method, and program product for storing a hardware manifest
Apparatus, methods, and program products are disclosed for storing a hardware manifest. One apparatus includes a processor and a memory that stores code executable by the processor. The code is executable by the processor to store a hardware manifest for an information handling device. The code is further executable by the processor to manage modification of the hardware manifest. Methods and computer program products that perform the functions of the apparatus are also disclosed.
Techniques for efficiently partitioning memory
Techniques are disclosed for allocating a global memory space defined within physical memory devices into strided memory space(s) (SMS) and partition memory space(s) (PMS). In an embodiment, a SMS is mapped across all of the devices, and a PMS is mapped to a subset of the devices to ensure resource isolation between separate PMSs. Typically, a memory space is allocated in unit sizes. When the locations mapped to most of the SMS align to an integer number of the unit size, a common boundary can be formed between the SMS and the one or more PMSs in each of the devices. Such a boundary can advantageously minimize a region of locations that are not available for allocation in the global memory spaces. In an embodiment, when a strided allocation is not an integer number of the unit size, a remainder is mapped to locations for one or more PMSs.
MULTI-VALUE MAPPING FOR OBJECT STORE
A method for mapping an object store may include storing a data entry within a mapping page for an object in the object store, wherein the data entry may include a key and a value, and the value may include an address for the object in the object store. The method may further include storing multiple data entries within the mapping page for multiple corresponding objects in the object store, wherein each data entry may include a key and one or more values for a corresponding object in the object store, and each value may include an address for the corresponding object in the object store. The data entries may be part of a mapping data structure which may include nodes, and each node may be stored within a mapping page.
High level instructions with lower-level assembly code style primitives within a memory appliance for accessing memory
A method of processing memory instructions including receiving a memory related command from a client system in communication with a memory appliance via a communication protocol, wherein the memory appliance comprises a processor, a memory unit controller and a plurality of memory devices coupled to said memory unit controller. The memory related command is translated by the processor into a plurality of commands that are formatted to perform prescribed data manipulation operations on data of the plurality of memory devices stored in data structures. The plurality of primitive commands is executed on data stored in the memory devices to produce a result, wherein the executing is performed by the memory unit controller. A direct memory transfer of the result is established over the communication protocol to a network.
Highly configurable memory architecture for partitioned global address space memory systems
A system and method for identifying from an address an appropriate target node and a location in that node that holds desired data related to that address is provided. The system and method includes a logical address generator that generates a logical address. The system and method includes a subspace index extraction module that extracts a subspace index from the logical address. The system and method includes a subspace configuration table that retrieves a plurality of parameters of the subspace index to locate the desired data.
TECHNOLOGIES FOR LIFECYCLE MANAGEMENT WITH REMOTE FIRMWARE
Technologies for lifecycle management include multiple computing devices in communication with a lifecycle management server. On boot, a computing device loads a lightweight firmware boot environment. The lightweight firmware boot environment connects to the lifecycle management server and downloads one or more firmware images for controllers of the computing device. The controllers may include baseboard management controllers, network interface controllers, solid-state drive controllers, or other controllers. The lifecycle management server may select firmware images and/or versions of firmware images based on the controllers or the computing device. The computing device installs each firmware image to a controller memory device coupled to a controller, and in use, each controller accesses the firmware image in the controller memory device. The controller memory device may be a DRAM device or a high-performance byte-addressable non-volatile memory. Other embodiments are described and claimed.
TECHNOLOGIES FOR PROVIDING SHARED MEMORY FOR ACCELERATOR SLEDS
Technologies for providing shared memory for accelerator sleds includes an accelerator sled to receive, with a memory controller, a memory access request from an accelerator device to access a region of memory. The request is to identify the region of memory with a logical address. Additionally, the accelerator sled is to determine from a map of logical addresses and associated physical address, the physical address associated with the region of memory. In addition, the accelerator sled is to route the memory access request to a memory device associated with the determined physical address.
Technologies for dynamically managing the reliability of disaggregated resources in a managed node
Technologies for dynamically managing the reliability of disaggregated resources in a managed node include a resource manager server. The resource manager server includes communication circuit to receive resource data from a set of disaggregated resources that indicates reliability of each disaggregated resource of the set of disaggregated resources and a node request to compose a managed node. The resource manager server further includes a compute engine to determine node parameters from the node request indicative of a target reliability of one or more disaggregated resources of the set of disaggregated resources to be included in the managed node, compose a managed node from the set of disaggregated resources that satisfies the node parameters by configuring the compute sled to utilize the disaggregated resources of the managed node for the execution of a workload, and monitor the disaggregated resources of the managed node for a failure.
Data connector with movable cover
A data connector to interface with a sled of a data center includes a main body, a plurality of guide shafts, and a cover. The main body includes electrical contacts. The guide shafts are associated with the main body, and each guide shaft extends along a corresponding longitudinal axis. The cover is coupled to the guide shafts such that the cover is slidable along the guide shafts in a direction defined by the longitudinal axes. The cover includes a movable door to provide protection to the electrical contacts of the main body when not in use.