A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.

A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.

The present disclosure relates to a system and method for optimizing switching of a DRAM bus using LLC. An embodiment of the disclosure includes sending a first type request from a first type queue to the second memory via the memory bus if a direction setting of the memory bus is in a first direction corresponding to the first type request, decrementing a current direction credit count by a first type transaction decrement value, if the decremented current direction credit count is greater than zero, sending another first type request to the second memory via the memory bus and decrementing the current direction credit count again by the first type transaction decrement value, and if the decremented current direction credit count is zero, switching the direction setting of the memory bus to a second direction and resetting the current direction credit count to a second type initial value.

The present disclosure relates to a system and method for optimizing switching of a DRAM bus using LLC. An embodiment of the disclosure includes sending a first type request from a first type queue to the second memory via the memory bus if a direction setting of the memory bus is in a first direction corresponding to the first type request, decrementing a current direction credit count by a first type transaction decrement value, if the decremented current direction credit count is greater than zero, sending another first type request to the second memory via the memory bus and decrementing the current direction credit count again by the first type transaction decrement value, and if the decremented current direction credit count is zero, switching the direction setting of the memory bus to a second direction and resetting the current direction credit count to a second type initial value.

Methods, systems, and devices that support efficient upload of firmware from memory are described. Multiple copies of a set of firmware may be stored across multiple planes of a memory device, such as with one respective copy within each of a set of planes. The copies may be staggered or otherwise offset in terms of page locations within the respective planes such that like-addressed pages within different planes store different subsets of the set of firmware. A controller may concurrently retrieve different subsets of the set of firmware, each of the different subsets included in a different copy, by concurrently retrieving the subsets stored at like-addressed pages within different memory planes. Upon loading the firmware code, the controller execute the firmware code to perform one or more further operations.

Methods, systems, and devices that support efficient upload of firmware from memory are described. Multiple copies of a set of firmware may be stored across multiple planes of a memory device, such as with one respective copy within each of a set of planes. The copies may be staggered or otherwise offset in terms of page locations within the respective planes such that like-addressed pages within different planes store different subsets of the set of firmware. A controller may concurrently retrieve different subsets of the set of firmware, each of the different subsets included in a different copy, by concurrently retrieving the subsets stored at like-addressed pages within different memory planes. Upon loading the firmware code, the controller execute the firmware code to perform one or more further operations.

Techniques described herein relate to systems and methods of data storage, and more particularly to providing layering of file system functionality on an object interface. In certain embodiments, file system functionality may be layered on cloud object interfaces to provide cloud-based storage while allowing for functionality expected from a legacy applications. For instance, POSIX interfaces and semantics may be layered on cloud-based storage, while providing access to data in a manner consistent with file-based access with data organization in name hierarchies. Various embodiments also may provide for memory mapping of data so that memory map changes are reflected in persistent storage while ensuring consistency between memory map changes and writes. For example, by transforming a ZFS file system disk-based storage into ZFS cloud-based storage, the ZFS file system gains the elastic nature of cloud storage.

Techniques described herein relate to systems and methods of data storage, and more particularly to providing layering of file system functionality on an object interface. In certain embodiments, file system functionality may be layered on cloud object interfaces to provide cloud-based storage while allowing for functionality expected from a legacy applications. For instance, POSIX interfaces and semantics may be layered on cloud-based storage, while providing access to data in a manner consistent with file-based access with data organization in name hierarchies. Various embodiments also may provide for memory mapping of data so that memory map changes are reflected in persistent storage while ensuring consistency between memory map changes and writes. For example, by transforming a ZFS file system disk-based storage into ZFS cloud-based storage, the ZFS file system gains the elastic nature of cloud storage.

A controller controls a memory device. The controller includes a buffer buffering one or more data chunks received from a host until the one or more data chunk is stored in the memory device, and a processor sorting and storing, according to data types of the one or more data chunks, the one or more data chunks buffered in the buffer in a plurality of memory regions of the memory device in a normal operation, the plurality of memory regions respectively corresponding to a plurality of data types. In response to a sudden power-off (SPO), the processor generates map data indicating a relationship between the one or more data chunks and the plurality of memory regions, generates a data string by merging the one or more data chunks, and stores the data string and the map data in a temporal memory region of the memory device.

A controller controls a memory device. The controller includes a buffer buffering one or more data chunks received from a host until the one or more data chunk is stored in the memory device, and a processor sorting and storing, according to data types of the one or more data chunks, the one or more data chunks buffered in the buffer in a plurality of memory regions of the memory device in a normal operation, the plurality of memory regions respectively corresponding to a plurality of data types. In response to a sudden power-off (SPO), the processor generates map data indicating a relationship between the one or more data chunks and the plurality of memory regions, generates a data string by merging the one or more data chunks, and stores the data string and the map data in a temporal memory region of the memory device.