Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.

A graphics pipeline includes a cache having cache lines that are configured to store data used to process frames in a graphics pipeline. The graphics pipeline is implemented using a processor that processes frames for the graphics pipeline using data stored in the cache. The processor processes a first frame and writes back a dirty cache line from the cache to a memory concurrently with processing of the first frame. The dirty cache line is retained in the cache and marked as clean subsequent to being written back to the memory. In some cases, the processor generates a hint that indicates a priority for writing back the dirty cache line based on a read command occupancy at a system memory controller.

A graphics pipeline includes a cache having cache lines that are configured to store data used to process frames in a graphics pipeline. The graphics pipeline is implemented using a processor that processes frames for the graphics pipeline using data stored in the cache. The processor processes a first frame and writes back a dirty cache line from the cache to a memory concurrently with processing of the first frame. The dirty cache line is retained in the cache and marked as clean subsequent to being written back to the memory. In some cases, the processor generates a hint that indicates a priority for writing back the dirty cache line based on a read command occupancy at a system memory controller.

Data is stored at a cache portion of a cache memory of a memory sub-system responsive to a request to perform a write operation to write the data. A duplicate copy of the data is stored at a write buffer portion of the cache memory. The cache memory is partitioned into the cache portion and the write buffer portion. An entry that maps a location of the duplicate copy of the data stored at the write buffer portion of the cache memory to a location of the data stored at the cache portion of the cache memory is recorded in a write buffer record.

Data is stored at a cache portion of a cache memory of a memory sub-system responsive to a request to perform a write operation to write the data. A duplicate copy of the data is stored at a write buffer portion of the cache memory. The cache memory is partitioned into the cache portion and the write buffer portion. An entry that maps a location of the duplicate copy of the data stored at the write buffer portion of the cache memory to a location of the data stored at the cache portion of the cache memory is recorded in a write buffer record.

A computer-implemented method for managing memory areas of a memory unit in a processing unit. The method includes determining, upon occurrence of a predefined event, a memory configuration profile according to which individual processes are in each case allowed to access individual memory areas of the memory unit, configuring the memory unit according to the determined memory configuration profile in such a way that the individual processes are in each case allowed to access individual memory areas of the memory unit, analyzing a performance of the processing unit while the particular processes are being executed in the processing unit and are accessing the individual memory areas according to the determined memory configuration profile, and providing a result of the analysis which describes the performance of the processing unit as a function of the determined memory configuration profile.

A computer-implemented method for managing memory areas of a memory unit in a processing unit. The method includes determining, upon occurrence of a predefined event, a memory configuration profile according to which individual processes are in each case allowed to access individual memory areas of the memory unit, configuring the memory unit according to the determined memory configuration profile in such a way that the individual processes are in each case allowed to access individual memory areas of the memory unit, analyzing a performance of the processing unit while the particular processes are being executed in the processing unit and are accessing the individual memory areas according to the determined memory configuration profile, and providing a result of the analysis which describes the performance of the processing unit as a function of the determined memory configuration profile.

An interface for coupling an agent to a fabric supports a set of coherent interconnect protocols and includes a global channel to communicate control signals to support the interface, a request channel to communicate messages associated with requests to other agents on the fabric, a response channel to communicate responses to other agents on the fabric, and a data channel to couple to communicate messages associated with data transfers to other agents on the fabric, where the data transfers include payload data.