A processing device in a memory sub-system identifies a first memory device and a second memory device and configures the second memory device with a zone namespace. The processing device identifies a first portion and a second portion of the first memory device, the first portion storing zone namespace metadata corresponding to the zone namespace on the second memory device. The processing device further exposes the second portion of the first memory device to a host system as a non-zoned addressable memory region.

A processing device in a memory sub-system identifies a first memory device and a second memory device and configures the second memory device with a zone namespace. The processing device identifies a first portion and a second portion of the first memory device, the first portion storing zone namespace metadata corresponding to the zone namespace on the second memory device. The processing device further exposes the second portion of the first memory device to a host system as a non-zoned addressable memory region.

In an embodiment, a processor includes at least one core and an interconnect that couples the at least one core and the cache memory. The interconnect is to operate at an interconnect frequency (f.sub.CL). The processor also includes a power management unit (PMU) including f.sub.CL logic to determine whether to adjust the f.sub.CL responsive to a Bayesian prediction value that is associated with scalability of a workload to be processed by the processor. The Bayesian prediction value may be determined based on one or more activity measures associated with the processor. Other embodiments are described and claimed.

In an embodiment, a processor includes at least one core and an interconnect that couples the at least one core and the cache memory. The interconnect is to operate at an interconnect frequency (f.sub.CL). The processor also includes a power management unit (PMU) including f.sub.CL logic to determine whether to adjust the f.sub.CL responsive to a Bayesian prediction value that is associated with scalability of a workload to be processed by the processor. The Bayesian prediction value may be determined based on one or more activity measures associated with the processor. Other embodiments are described and claimed.

A processor implementing techniques to supporting fault information delivery is disclosed. In one embodiment, the processor includes a memory controller unit to access an enclave page cache (EPC) and a processor core coupled to the memory controller unit. The processor core to detect a fault associated with accessing the EPC and generate an error code associated with the fault. The error code reflects an EPC-related fault cause. The processor core is further to encode the error code into a data structure associated with the processor core. The data structure is for monitoring a hardware state related to the processor core.

A processor implementing techniques to supporting fault information delivery is disclosed. In one embodiment, the processor includes a memory controller unit to access an enclave page cache (EPC) and a processor core coupled to the memory controller unit. The processor core to detect a fault associated with accessing the EPC and generate an error code associated with the fault. The error code reflects an EPC-related fault cause. The processor core is further to encode the error code into a data structure associated with the processor core. The data structure is for monitoring a hardware state related to the processor core.

The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the present disclosure can include an array of memory cells configured to store multiple cache entries per page of memory cells; and sense circuitry configured to determine whether cache data corresponding to a request from a cache controller is located at a location in the array corresponding to the request, and return a response to the cache controller indicating whether cache data is located at the location in the array corresponding to the request.

The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the present disclosure can include an array of memory cells configured to store multiple cache entries per page of memory cells; and sense circuitry configured to determine whether cache data corresponding to a request from a cache controller is located at a location in the array corresponding to the request, and return a response to the cache controller indicating whether cache data is located at the location in the array corresponding to the request.

The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the present disclosure can include an array of memory cells configured to store multiple cache entries per page of memory cells; and sense circuitry configured to determine whether cache data corresponding to a request from a cache controller is located at a location in the array corresponding to the request, and return a response to the cache controller indicating whether cache data is located at the location in the array corresponding to the request.

A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower. Methods provided here may be extended for systems that have more than two cache levels.