G06F12/0864

System and method for a hash table and data storage and access using the same
11691896 · 2023-07-04 · ·

The present teaching relates to method, system, medium, and implementations for storage management. A hash table is constructed, having an index file having one or more slots, each of which includes one or more buckets. Each bucket stores one or more types of records, including a direct record, an indirect record, and a forwarding record. A direct record stores data directly in a bucket of a slot of the index file. When a storage request is received related to some relevant data, the request is handled based on the constructed hash table.

Adaptive cache

Described apparatuses and methods form adaptive cache lines having a configurable capacity from hardware cache lines having a fixed capacity. The adaptive cache lines can be formed in accordance with a programmable cache-line parameter. The programmable cache-line parameter can specify a capacity for the adaptive cache lines. The adaptive cache lines may be formed by combining respective groups of fixed-capacity hardware cache lines. The quantity of fixed-capacity hardware cache lines included in respective adaptive cache lines may be based on the programmable cache-line parameter. The programmable cache-line parameter can be selected in accordance with characteristics of the cache workload.

Adaptive cache

Described apparatuses and methods form adaptive cache lines having a configurable capacity from hardware cache lines having a fixed capacity. The adaptive cache lines can be formed in accordance with a programmable cache-line parameter. The programmable cache-line parameter can specify a capacity for the adaptive cache lines. The adaptive cache lines may be formed by combining respective groups of fixed-capacity hardware cache lines. The quantity of fixed-capacity hardware cache lines included in respective adaptive cache lines may be based on the programmable cache-line parameter. The programmable cache-line parameter can be selected in accordance with characteristics of the cache workload.

MEMORY ARRAY PAGE TABLE WALK
20250231885 · 2025-07-17 ·

An example memory array page table walk can include using an array of memory cells configured to store a page table. The page table walk can include using sensing circuitry coupled to the array. The page table walk can include using a controller coupled to the array. The controller can be configured to operate the sensing circuitry to determine a physical address of a portion of data by accessing the page table in the array of memory cells. The controller can be configured to operate the sensing circuitry to cause storing of the portion of data in a buffer.

MEMORY ARRAY PAGE TABLE WALK
20250231885 · 2025-07-17 ·

An example memory array page table walk can include using an array of memory cells configured to store a page table. The page table walk can include using sensing circuitry coupled to the array. The page table walk can include using a controller coupled to the array. The controller can be configured to operate the sensing circuitry to determine a physical address of a portion of data by accessing the page table in the array of memory cells. The controller can be configured to operate the sensing circuitry to cause storing of the portion of data in a buffer.

Universal pointers for data exchange in a computer system having independent processors
11544069 · 2023-01-03 · ·

A system, method and apparatus to facilitate data exchange via pointers. For example, in a computing system having a first processor and a second processor that is separate and independent from the first processor, the first processor can run a program configured to use a pointer identifying a virtual memory address having an ID of an object and an offset within the object. The first processor can use the virtual memory address to store data at a memory location in the computing system and/or identify a routine at the memory location for execution by the second processor. After the pointer is communicated from the first processor to the second processor, the second processor can access the same memory location identified by the virtual memory address. The second processor may operate on the data stored at the memory location or load the routine from the memory location for execution.

Convertible force latching system

A convertible force latching system includes two complementary connector bodies. Each connector body has a first mating face under which two series of magnets oriented alternating directions. A moving portion of the latching system allows the connector bodies and the magnets within to alter their alignment by the interaction of a user along a predetermined motion path. In a first arrangement, the series of magnets are aligned with such that the magnets of one connector body are attracted to the magnets of the other connector body. When the user actuation shifts the moving portion, the second arrangement positions the series of magnets such that they are aligned such that the magnets of one connector body are repelled to the magnets of the other connector body.

Convertible force latching system

A convertible force latching system includes two complementary connector bodies. Each connector body has a first mating face under which two series of magnets oriented alternating directions. A moving portion of the latching system allows the connector bodies and the magnets within to alter their alignment by the interaction of a user along a predetermined motion path. In a first arrangement, the series of magnets are aligned with such that the magnets of one connector body are attracted to the magnets of the other connector body. When the user actuation shifts the moving portion, the second arrangement positions the series of magnets such that they are aligned such that the magnets of one connector body are repelled to the magnets of the other connector body.

Command result caching for building application container images
11537523 · 2022-12-27 · ·

Implementations of the disclosure provide systems and methods for receiving, by a processing device, a request for an application image. A sequence of commands associated with the application image and a value of a parameter associated with the sequence of commands is received. Responsive to determining that the sequence of commands has been previously executed with the value of the parameter, the processing device retrieves, from a cache, a result of executing the sequence with the value of the parameter. The application image is built using the first result of executing the sequence.

Command result caching for building application container images
11537523 · 2022-12-27 · ·

Implementations of the disclosure provide systems and methods for receiving, by a processing device, a request for an application image. A sequence of commands associated with the application image and a value of a parameter associated with the sequence of commands is received. Responsive to determining that the sequence of commands has been previously executed with the value of the parameter, the processing device retrieves, from a cache, a result of executing the sequence with the value of the parameter. The application image is built using the first result of executing the sequence.