Patent classifications
G06F12/0866
METHOD AND SYSTEM FOR CONSTRUCTING PERSISTENT MEMORY INDEX IN NON-UNIFORM MEMORY ACCESS ARCHITECTURE
A method for constructing a persistent memory index in a non-uniform memory access architecture includes: maintaining partial persistent views in a persistent memory and maintaining a global volatile view in a DRAM; an underlying persistent memory index processing a request in a foreground thread when cold data is accessed; when hot data is accessed, reading a key-value pair for a piece of hot data in the global volatile view in response to a query operation carried in the request, and in response to an insert/update/delete operation carried in the request, updating a local partial persistent view and the global volatile view; and in response to a hotspot migration, a background thread generating new partial persistent views and a new global volatile view, and recycling the partial persistent views and the global volatile view for old hot data into the underlying persistent memory index.
METHODS AND APPARATUSES FOR DYNAMICALLY CHANGING DATA PRIORITY IN A CACHE
Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.
Data transfer in port switch memory
The present disclosure includes apparatuses and methods related to data transfer in memory. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein a first number of commands are executed to transfer data between the first number of memory devices and the host via the first number of ports and a second number of commands are executed to transfer data between the first number of memory device and the second number of memory device via the second number of ports.
Distributed numeric sequence generation
Various embodiments of a distributed numeric sequence generation system and method are described. In particular, some embodiments provide high-scale, high-availability, low-cost and low-maintenance numeric sequence generation in a non-Relational Database Management System (“non-RBMS”) system by sacrificing monotonicity. The distributed numeric sequence generation system comprises a plurality of hosts, wherein individual hosts implement a cache for caching a plurality of numeric sequences. A host can access master numeric sequence data at a separate system to obtain values for numeric sequences to store in its cache. A host can receive a request from a client for values of a numeric sequence, and provide to the client the values for the numeric sequence from its cache. Some embodiments of the distributed numeric sequence generation system and method are also equipped to vend recyclable and bounded numeric sequences.
Semiconductor storage device with volatile and nonvolatile memories to allocate blocks to a memory and release allocated blocks
A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
ADJUSTABLE TIMER COMPONENT FOR SEMICONDUCTOR DEVICES
Systems, apparatuses, and methods related to an adjustable timer component are described. A memory device includes, a memory controller coupled to the memory device comprising an adjustable timer component. The adjustable timer component is configured to receive a timer generation request and, responsive to receiving the request, store in a cache an active timer entry corresponding to a particular first address, generate a timer corresponding to an active timer entry and the particular first address, and monitor the timer to determine when the timer expires. Responsive to the expiration of the timer, dequeue the timer entry and invalidate the timer entry stored in the cache. The memory device can also include command logic configured to, prior to issuing a second command, query the cache of the adjustable timer component to determine if the cache includes an active timer entry corresponding to the particular second address.
Reliable delivery of event notifications from a distributed file system
Embodiments include a method for fault tolerance in the delivery of event information within a file system cluster. One or more processors to determine event information associated with file system activity performed by a node of the cluster. The one or more processors add the event information to an event log buffer in memory. The one or more processors receive a first log sequence number (LSN) associated with flushing of recovery information from a recovery log buffer. The one or more processors determine the event information in the event log buffer having a log sequence number less than or equal to the first log sequence number, and determining the event information includes log sequence numbers less than or equal to the first log sequence number, the one or more processors flush the corresponding event information from the event log buffer to disk storage.
Reliable delivery of event notifications from a distributed file system
Embodiments include a method for fault tolerance in the delivery of event information within a file system cluster. One or more processors to determine event information associated with file system activity performed by a node of the cluster. The one or more processors add the event information to an event log buffer in memory. The one or more processors receive a first log sequence number (LSN) associated with flushing of recovery information from a recovery log buffer. The one or more processors determine the event information in the event log buffer having a log sequence number less than or equal to the first log sequence number, and determining the event information includes log sequence numbers less than or equal to the first log sequence number, the one or more processors flush the corresponding event information from the event log buffer to disk storage.
Method, electronic device and computer program product for storing data
Techniques for storing data involve estimating a hit ratio of a digest cache associated with a target storage device, the digest cache recording a digest of data that is stored in the target storage device after preprocessing; generating, according to a determination that the hit ratio is lower than a predetermined threshold, a digest for target data to be stored and performing the preprocessing; and storing, according to a determination that the digest of the target data is missing in the digest cache, the preprocessed target data in the target storage device, and recording the digest of the target data in the digest cache. Such techniques can achieve good system performance in both cases of high data repetition and low data repetition.
Instance Deployment Method, Instance Management Node, Computing Node, and Computing Device
In a method, an instance management node receives a request for creating a service instance; the instance management node obtains a cache configuration corresponding to the service instance; and the instance management node creates the service instance on a computing node, and creates a cache instance on the computing node based on the cache configuration. In this way, the service instance may provide a service by using the matched cache instance.