Examples described herein relate to circuitry, when operational, configured to: store records of memory accesses to a memory device by at least one requester based on a configuration, wherein the configuration is to specify a duration of memory access capture. In some examples, the at least one requester comprises one or more workloads running on one or more processors. In some examples, the configuration is to specify collection of one or more of: physical address ranges or read or write access type.

Examples described herein relate to circuitry, when operational, configured to: store records of memory accesses to a memory device by at least one requester based on a configuration, wherein the configuration is to specify a duration of memory access capture. In some examples, the at least one requester comprises one or more workloads running on one or more processors. In some examples, the configuration is to specify collection of one or more of: physical address ranges or read or write access type.

A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.

A method and a device for rapidly searching a cache are provided. The method for rapidly searching a cache includes: translating a source identifier (SID) to a domain identifier (DID) according to an extended flag from the software by searching a context cache, wherein the extended flag indicates that a current context entry stored in the context cache is a normal context entry or an extended context entry.

Examples of systems and method described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.

Examples of systems and method described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.

A circuit and method for data transmission, and a storage apparatus are provided. A mode register decoding module is configured to generate a mode register unselected enable signal, a mode register read enable signal, or a mode register write enable signal according to received mode register address information, a mode register read control signal, or a mode register write control signal. A mode register read-write module is configured to: cache data on data line according to mode register write enable signal in write state, and output selected data and unselected data after setting the unselected data to zero according to the mode register read enable signal and the mode register unselected enable signal in a read state. The logic gate module is configured to calculate an OR value of the data outputted by each mode register read-write module in the read state and output a calculation result.

Managing data stored in a cache using a reinforcement learning agent may include: determining a set of current state observations with respect to a cache, wherein the set of current state observations is determined based on historical cache accesses to the cache; inputting the set of current state observations into an actor network of a reinforcement learning (RL) agent to obtain an action output by the actor network, wherein the RL agent is configured to manage data stored at the cache; inputting the set of current state observations and the action into a critic network of the RL agent to obtain a score corresponding to the action from the critic network; causing the RL agent to perform the action with respect to managing the data stored at the cache; using the score to update the actor network; and using a reward corresponding to the action to update the critic network.

Managing data stored in a cache using a reinforcement learning agent may include: determining a set of current state observations with respect to a cache, wherein the set of current state observations is determined based on historical cache accesses to the cache; inputting the set of current state observations into an actor network of a reinforcement learning (RL) agent to obtain an action output by the actor network, wherein the RL agent is configured to manage data stored at the cache; inputting the set of current state observations and the action into a critic network of the RL agent to obtain a score corresponding to the action from the critic network; causing the RL agent to perform the action with respect to managing the data stored at the cache; using the score to update the actor network; and using a reward corresponding to the action to update the critic network.

The present technique provides an apparatus and method for caching data. The apparatus has a cache storage to cache data associated with memory addresses, a first interface to receive access requests, where each access request is a request to access data at a memory address indicated by that access request, and a second interface to couple to a memory controller used to control access to memory. Further, cache control circuitry is used to control allocation of data into the cache storage in accordance with a power consumption based allocation policy that seeks to select which data is cached in the cache storage with the aim of conserving power associated with accesses to the memory via the second interface. A given access request considered by the cache control circuitry is provided with associated cache hint information providing one or more usage indications for given data at the memory address indicated by that given access request, and the cache control circuitry is arranged to reference the associated cache hint information when applying the power consumption based allocation policy to determine whether to cache the given data in the cache storage.