Systems, apparatuses and methods of adaptively controlling a cache operating voltage are provided that comprise receiving indications of a plurality of cache usage amounts. Each cache usage amount corresponds to an amount of data to be accessed in a cache by one of a plurality of portions of a data processing application. The plurality of cache usage amounts are determining based on the received indications of the plurality of cache usage amounts. A voltage level applied to the cache is adaptively controlled based on one or more of the plurality of determined cache usage amounts. Memory access to the cache is controlled to be directed to a non-failing portion of the cache at the applied voltage level.

Various embodiments described herein provide for a memory sub-system read operation or a memory sub-system write operation that can be requested by a host system and involves performing a multi-level (e.g., two-level) pointer dereferencing internally within the memory sub-system. Such embodiments can at least reduce the number of read operations that a host system sends to a memory sub-system to perform a multi-level dereferencing operation.

Various embodiments described herein provide for a memory sub-system read operation or a memory sub-system write operation that can be requested by a host system and involves performing a multi-level (e.g., two-level) pointer dereferencing internally within the memory sub-system. Such embodiments can at least reduce the number of read operations that a host system sends to a memory sub-system to perform a multi-level dereferencing operation.

Incoming host data is programmed to a first set of data blocks indicated by a first cursor of a memory sub-system. The first set of blocks is associated with a first write mode. A determination is made that a second set of blocks associated with a second write mode is available to store the incoming host data prior to closing one or more of the first set of blocks. The incoming host data is programmed to the second set of blocks in view of a second cursor of the memory sub-system. A media management operation is performed to close the one or more of the first set of blocks.

Incoming host data is programmed to a first set of data blocks indicated by a first cursor of a memory sub-system. The first set of blocks is associated with a first write mode. A determination is made that a second set of blocks associated with a second write mode is available to store the incoming host data prior to closing one or more of the first set of blocks. The incoming host data is programmed to the second set of blocks in view of a second cursor of the memory sub-system. A media management operation is performed to close the one or more of the first set of blocks.

In various embodiments, methods and systems, for implementing modular data operations, are provided. A data access request, associated with data, is received at a data access component. The data access component selectively implements modular data operations functionality based on configuration settings. A translation table associated with a working set is accessed, based on the configuration settings of the data access component, to determine a location for executing the data access request. The data access request is executed using the cache store or a backing store associated with the working set. The data access request is executed using the location that is determined using the translation table of the working set. The data access request is executed using the cache store when the data is cached in the cache store and the data access requested is executed based on the backing store when the data is un-cached in the cache store.

Systems and methods to predict and prefetch a cache access based on a delta pattern are disclosed. The delta pattern may comprise a sequence of differences between first and second cache accesses within a page. In one example, a processor includes execution circuitry to extract a delta history corresponding to a delta pattern associated with one or more previous cache accesses corresponding to a page of memory. The processor execution circuitry further generates a bucketed delta history based on the delta history corresponding to the page of memory and selects a prediction entry based on the bucketed delta history. The processor execution circuitry then identifies one or more prefetch candidates based on a confidence threshold, with the confidence threshold indicating one or more probable delta patterns, and filters the one or more prefetch candidates. Prefetch circuitry of the processor then predicts and prefetches a cache access based the one or more prefetch candidates.

Systems and methods to predict and prefetch a cache access based on a delta pattern are disclosed. The delta pattern may comprise a sequence of differences between first and second cache accesses within a page. In one example, a processor includes execution circuitry to extract a delta history corresponding to a delta pattern associated with one or more previous cache accesses corresponding to a page of memory. The processor execution circuitry further generates a bucketed delta history based on the delta history corresponding to the page of memory and selects a prediction entry based on the bucketed delta history. The processor execution circuitry then identifies one or more prefetch candidates based on a confidence threshold, with the confidence threshold indicating one or more probable delta patterns, and filters the one or more prefetch candidates. Prefetch circuitry of the processor then predicts and prefetches a cache access based the one or more prefetch candidates.

Technologies are generally described for methods and systems effective to access data in a cache. In an example, a method to access data in a cache may include processing a first request for data at a first memory address related to first data in a memory. The method may further include retrieving the first data from the memory. The method may further include storing the first data in a first cache line in the cache. The method may further include processing a second request for data at a second memory address related to second data in the memory. The method may further include retrieving the second data from the memory. The method may further include selecting a second cache line in the cache to store the second data based on the storage of the first data. The method may further include storing the second data in the second cache line.

Technologies are generally described for methods and systems effective to access data in a cache. In an example, a method to access data in a cache may include processing a first request for data at a first memory address related to first data in a memory. The method may further include retrieving the first data from the memory. The method may further include storing the first data in a first cache line in the cache. The method may further include processing a second request for data at a second memory address related to second data in the memory. The method may further include retrieving the second data from the memory. The method may further include selecting a second cache line in the cache to store the second data based on the storage of the first data. The method may further include storing the second data in the second cache line.