G06F12/0891

APPROACH FOR SUPPORTING MEMORY-CENTRIC OPERATIONS ON CACHED DATA
20230021492 · 2023-01-26 ·

A technical solution to the technical problem of how to support memory-centric operations on cached data uses a novel memory-centric memory operation that invokes write back functionality on cache controllers and memory controllers. The write back functionality enforces selective flushing of dirty, i.e., modified, cached data that is needed for memory-centric memory operations from caches to the completion level of the memory-centric memory operations, and updates the coherence state appropriately at each cache level. The technical solution ensures that commands to implement the selective cache flushing are ordered before the memory-centric memory operation at the completion level of the memory-centric memory operation.

APPROACH FOR SUPPORTING MEMORY-CENTRIC OPERATIONS ON CACHED DATA
20230021492 · 2023-01-26 ·

A technical solution to the technical problem of how to support memory-centric operations on cached data uses a novel memory-centric memory operation that invokes write back functionality on cache controllers and memory controllers. The write back functionality enforces selective flushing of dirty, i.e., modified, cached data that is needed for memory-centric memory operations from caches to the completion level of the memory-centric memory operations, and updates the coherence state appropriately at each cache level. The technical solution ensures that commands to implement the selective cache flushing are ordered before the memory-centric memory operation at the completion level of the memory-centric memory operation.

Bottom-up Pre-emptive Cache Update in a Multi-level Redundant Cache System
20230022351 · 2023-01-26 ·

Embodiments for providing cache updates in a hierarchical multi-node system, through a service component between a lower level component and a next higher level component by maintaining a ledger storing an incrementing entry number indicating a present state of the datasets in a cache of the lower level component. The service component receives a data request to the lower level component from the higher level component including an appended last entry number accessed by the higher level component, and determines if the appended last entry number matches a current entry number in the ledger for any requested dataset, wherein no match indicates that at least some data in the higher level component cache is stale. In which case, it sends updated data information for the stale data to the higher level component, while the higher level component invalidates its cache entries and updates the appended last entry number to match a current entry number in the ledger.

Bottom-up Pre-emptive Cache Update in a Multi-level Redundant Cache System
20230022351 · 2023-01-26 ·

Embodiments for providing cache updates in a hierarchical multi-node system, through a service component between a lower level component and a next higher level component by maintaining a ledger storing an incrementing entry number indicating a present state of the datasets in a cache of the lower level component. The service component receives a data request to the lower level component from the higher level component including an appended last entry number accessed by the higher level component, and determines if the appended last entry number matches a current entry number in the ledger for any requested dataset, wherein no match indicates that at least some data in the higher level component cache is stale. In which case, it sends updated data information for the stale data to the higher level component, while the higher level component invalidates its cache entries and updates the appended last entry number to match a current entry number in the ledger.

COHERENCE-BASED ATTACK DETECTION
20230022096 · 2023-01-26 ·

While an application or a virtual machine (VM) is running, a device tracks accesses to cache lines to detect access patterns that indicate security attacks, such as cache-based side channel attacks or row hammer attacks. To enable the device to detect accesses to cache lines, the device is connected to processors via a coherence interconnect, and the application/VM data is stored in a local memory of the device. The device collects the cache lines of the application/VM data that are accessed while the application/VM is running into a buffer and the buffer is analyzed for access patterns that indicate security attacks.

COHERENCE-BASED ATTACK DETECTION
20230022096 · 2023-01-26 ·

While an application or a virtual machine (VM) is running, a device tracks accesses to cache lines to detect access patterns that indicate security attacks, such as cache-based side channel attacks or row hammer attacks. To enable the device to detect accesses to cache lines, the device is connected to processors via a coherence interconnect, and the application/VM data is stored in a local memory of the device. The device collects the cache lines of the application/VM data that are accessed while the application/VM is running into a buffer and the buffer is analyzed for access patterns that indicate security attacks.

DATA MANAGEMENT METHOD AND COMPUTER-READABLE RECORDING MEDIUM STORING DATA MANAGEMENT PROGRAM
20230229597 · 2023-07-20 · ·

A data management method causes a computer to execute processing including: creating, when a predetermined data processing program performs data processing, based on an access frequency to a data store, high-frequency state item list information obtained by listing high-frequency state items of which the access frequency is high; determining, when state information that includes a value of the high-frequency state item is written to the data store, whether or not the state information corresponds to the high-frequency state item with reference to the high-frequency state item list information; grouping and writing pieces of the state information of a plurality of the high-frequency state item.

DATA MANAGEMENT METHOD AND COMPUTER-READABLE RECORDING MEDIUM STORING DATA MANAGEMENT PROGRAM
20230229597 · 2023-07-20 · ·

A data management method causes a computer to execute processing including: creating, when a predetermined data processing program performs data processing, based on an access frequency to a data store, high-frequency state item list information obtained by listing high-frequency state items of which the access frequency is high; determining, when state information that includes a value of the high-frequency state item is written to the data store, whether or not the state information corresponds to the high-frequency state item with reference to the high-frequency state item list information; grouping and writing pieces of the state information of a plurality of the high-frequency state item.

Integration of application indicated minimum time to cache to least recently used track demoting schemes in a cache management system of a storage controller

A minimum retention time in cache is indicated for a first plurality of tracks, where no minimum retention time is indicated for a second plurality of tracks. A cache management application demotes a track of the first plurality of tracks from the cache, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the cache and the track has been in the cache for a time that exceeds the minimum retention time.

Integration of application indicated minimum time to cache to least recently used track demoting schemes in a cache management system of a storage controller

A minimum retention time in cache is indicated for a first plurality of tracks, where no minimum retention time is indicated for a second plurality of tracks. A cache management application demotes a track of the first plurality of tracks from the cache, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the cache and the track has been in the cache for a time that exceeds the minimum retention time.