A system for updating a hypercube includes an interface and a processor. The interface is configured to receive an indication to update a cell of the hypercube. The processor is configured to determine a primary dimension value associated with the cell; determine a group of dependencies based at least in part on the primary dimension value, wherein a dependency of the group of dependencies comprises one or more primary dimension values and a pattern; for the dependency of the group of dependencies, determine a set of source locations based at least in part on the one or more primary dimension values and the pattern; and mark the set of source locations as invalid.

A system for updating a hypercube includes an interface and a processor. The interface is configured to receive an indication to update a cell of the hypercube. The processor is configured to determine a primary dimension value associated with the cell; determine a group of dependencies based at least in part on the primary dimension value, wherein a dependency of the group of dependencies comprises one or more primary dimension values and a pattern; for the dependency of the group of dependencies, determine a set of source locations based at least in part on the one or more primary dimension values and the pattern; and mark the set of source locations as invalid.

A memory system of an embodiment includes a nonvolatile memory, a primary cache memory, a secondary cache memory, and a processor. The processor performs address conversion by using logical-to-physical address conversion information relating to data to be addressed in the nonvolatile memory. Based on whether first processing is performed on the nonvolatile memory or second processing is performed on the nonvolatile memory, the processor controls to store whether the logical-to-physical address conversion information relating to the first processing to be in the primary cache memory as cache data or logical-to-physical address conversion information relating to the second processing to be in the secondary cache memory as cache data.

A memory system of an embodiment includes a nonvolatile memory, a primary cache memory, a secondary cache memory, and a processor. The processor performs address conversion by using logical-to-physical address conversion information relating to data to be addressed in the nonvolatile memory. Based on whether first processing is performed on the nonvolatile memory or second processing is performed on the nonvolatile memory, the processor controls to store whether the logical-to-physical address conversion information relating to the first processing to be in the primary cache memory as cache data or logical-to-physical address conversion information relating to the second processing to be in the secondary cache memory as cache data.

A drive placement or placement functionality can enable initial copies of data to be placed on a drive in reclaim unit (HRUs) in a manner which is probabilistically more efficient from a garbage collection (GC) perspective and leverages knowledge of a host or application using the data. The placement functionality enables the advantages of fine-grained placement functionality while simultaneously allowing a storage device or storage drive to maintain NAND or other management responsibility, and not allocate that responsibility to an application or host device using the device.

A drive placement or placement functionality can enable initial copies of data to be placed on a drive in reclaim unit (HRUs) in a manner which is probabilistically more efficient from a garbage collection (GC) perspective and leverages knowledge of a host or application using the data. The placement functionality enables the advantages of fine-grained placement functionality while simultaneously allowing a storage device or storage drive to maintain NAND or other management responsibility, and not allocate that responsibility to an application or host device using the device.

A method for page management in a memory system may include allocating a page of a mirror memory, copying a valid page from a block of device memory at a device to the page of the mirror memory, remapping the valid page from the block of device memory to the mirror memory, and modifying the block of device memory. The method may further include copying the valid page from the mirror memory to a free page at the device, and remapping the valid page from the mirror memory to the free page at the device. The remapping may be performed using a memory coherent interface. The method may further include deallocating a portion of the mirror memory associated with the valid page based on copying the valid page from the mirror memory.

A method for page management in a memory system may include allocating a page of a mirror memory, copying a valid page from a block of device memory at a device to the page of the mirror memory, remapping the valid page from the block of device memory to the mirror memory, and modifying the block of device memory. The method may further include copying the valid page from the mirror memory to a free page at the device, and remapping the valid page from the mirror memory to the free page at the device. The remapping may be performed using a memory coherent interface. The method may further include deallocating a portion of the mirror memory associated with the valid page based on copying the valid page from the mirror memory.

An apparatus includes multiple processors including respective cache memories, the cache memories configured to cache cache-entries for use by the processors. At least a processor among the processors includes cache management logic that is configured to (i) receive, from one or more of the other processors, cache-invalidation commands that request invalidation of specified cache-entries in the cache memory of the processor (ii) mark the specified cache-entries as intended for invalidation but defer actual invalidation of the specified cache-entries, and (iii) upon detecting a synchronization event associated with the cache-invalidation commands, invalidate the cache-entries that were marked as intended for invalidation.

In one embodiment, an apparatus includes a processor comprising an address translation cache (ATC); a shared work queue (SWQ) associated with the ATC, and a port to couple to a host processor over a Peripheral Component Interconnect Express (PCIe)-based link. The apparatus also includes circuitry to receive address translation information from a memory management unit of the host processor that includes virtual memory address to physical memory address translations, store the address translation information in the ATC, receive an invalidation command from the host processor indicating an invalidation of address translation information stored in the ATC, modify the address translation information in the ATC based on the invalidation command, and store completion data in a memory location indicated by the invalidation command.