A device for writing data to a memory, the device including: a first write buffer having a first data width that matches a width of write data included in a write request and wherein the first write buffer is configured to store the write data as first data; a second write buffer having a second data width that matches a data width of the memory and is greater than the first data width; and a controller configured to, based on a write address included in the write request and an address of the second data stored in the second write buffer, write the first data stored in the first write buffer to the second write buffer and write the second data stored in the second write buffer to the memory.

Methods, systems, and devices for maintaining sequentiality for media management of a memory sub-system are described. A plurality of read commands in connection with a set of media management operations for a plurality of transfer units are issued according to a read sequence. A plurality of entries associated with the set of media management operations are stored. A plurality of write commands in connection with the set of media management operations are issued based on the plurality of entries of the read sequence.

Methods, systems, and devices for maintaining sequentiality for media management of a memory sub-system are described. A plurality of read commands in connection with a set of media management operations for a plurality of transfer units are issued according to a read sequence. A plurality of entries associated with the set of media management operations are stored. A plurality of write commands in connection with the set of media management operations are issued based on the plurality of entries of the read sequence.

A data storage system with interconnected compute nodes includes a shared memory with volatile and non-volatile portions. Data tracks evicted from the volatile portion are moved to the non-volatile portion based on a cache-miss interarrival rate threshold that is calculated based on capacity and fall-through time of the non-volatile portion of the shared memory. Data extents on non-volatile drives are characterized based on dominant modes of extent-level cache-miss interarrival histograms generated using countdown timers of most recent backend accesses of sub-extents. The dominant mode of the extent in which a backend track evicted from the volatile portion of the shared memory resides is compared with the threshold in order to determine whether to move the backend track to the non-volatile portion of the shared memory.

A data storage system with interconnected compute nodes includes a shared memory with volatile and non-volatile portions. Data tracks evicted from the volatile portion are moved to the non-volatile portion based on a cache-miss interarrival rate threshold that is calculated based on capacity and fall-through time of the non-volatile portion of the shared memory. Data extents on non-volatile drives are characterized based on dominant modes of extent-level cache-miss interarrival histograms generated using countdown timers of most recent backend accesses of sub-extents. The dominant mode of the extent in which a backend track evicted from the volatile portion of the shared memory resides is compared with the threshold in order to determine whether to move the backend track to the non-volatile portion of the shared memory.

A tile-based graphics system has a rendering space sub-divided into a plurality of tiles which are to be processed. Graphics data items, such as parameters or texels, are fetched into a cache for use in processing one of the tiles. Indicators are determined for the graphics data items, whereby the indicator for a graphics data item indicates the number of tiles with which that graphics data item is associated. The graphics data items are evicted from the cache in accordance with the indicators of the graphics data items. For example, the indicator for a graphics data item may be a count of the number of tiles with which that graphics data item is associated, whereby the graphics data item(s) with the lowest count(s) is (are) evicted from the cache.

A tile-based graphics system has a rendering space sub-divided into a plurality of tiles which are to be processed. Graphics data items, such as parameters or texels, are fetched into a cache for use in processing one of the tiles. Indicators are determined for the graphics data items, whereby the indicator for a graphics data item indicates the number of tiles with which that graphics data item is associated. The graphics data items are evicted from the cache in accordance with the indicators of the graphics data items. For example, the indicator for a graphics data item may be a count of the number of tiles with which that graphics data item is associated, whereby the graphics data item(s) with the lowest count(s) is (are) evicted from the cache.

Method and apparatus implementing smart store operations with conditional ownership requests. One aspect includes a method implemented in a multi-core processor, the method comprises: receiving a conditional read for ownership (CondRFO) from a requester in response to an execution of an instruction to modify a target cache line (CL) with a new value, the CondRFO identifying the target CL and the new value; determining from a local cache a local CL corresponding to the target CL; determining a local value from the local CL; comparing the local value with the new value; setting a coherency state of the local CL to (S)hared when the local value is same as the new value; setting the coherency state of the local CL to (I)nvalid when the local value is different than the new value; and sending a response and a copy of the local CL to the requester. Other embodiments include an apparatus configured to perform the actions of the methods.

Method and apparatus implementing smart store operations with conditional ownership requests. One aspect includes a method implemented in a multi-core processor, the method comprises: receiving a conditional read for ownership (CondRFO) from a requester in response to an execution of an instruction to modify a target cache line (CL) with a new value, the CondRFO identifying the target CL and the new value; determining from a local cache a local CL corresponding to the target CL; determining a local value from the local CL; comparing the local value with the new value; setting a coherency state of the local CL to (S)hared when the local value is same as the new value; setting the coherency state of the local CL to (I)nvalid when the local value is different than the new value; and sending a response and a copy of the local CL to the requester. Other embodiments include an apparatus configured to perform the actions of the methods.

A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.