Disclosed is a method of managing memory of a virtual machine (VM), including receiving, at a physical input-output memory management unit (IOMMU) of a processing device operating the VM, a request from a VM IOMMU for VM memory address translation for a VM peripheral component interconnect (PCI) device created on the VM; determining, by the physical IOMMU, a corresponding VM memory address translation result based on the request as received and a memory translation table; and transmitting, by the physical IOMMU to the VM IOMMU, the corresponding VM memory address translation result for servicing the request for VM memory address translation of the VM PCI device.

Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.

At least one example embodiment provides a programmable logic device comprising: a plurality of reconfigurable slots programmed to execute functions requested by a plurality of users, the plurality of reconfigurable slots allocated among the plurality of users; a memory divided into a plurality of memory segments, the plurality of memory segments allocated among the plurality of reconfigurable slots; and a memory management circuit configured to dynamically adjust the plurality of memory segments based on at least one of activity or memory requirements of the plurality of reconfigurable slots.

A computing device includes a host processor to execute a host driver to create a host-side interface, the host-side interface emulating a first Ethernet interface, assign the host-side interface a first medium access control (MAC) address and a first Internet Protocol (IP) address. Memory components are disposed on a substrate. A memory channel network (MCN) processor is disposed on the substrate and coupled between the memory components and the host processor. The MCN processor is to execute an MCN driver to create a MCN-side interface, the MCN-side interface emulating a second Ethernet interface. The MCN processor is to assign the MCN-side interface a second MAC address and a second IP address, which identify the MCN processor as a MCN network node to the host processor.

A Key-Value (KV) storage device is disclosed. The KV storage device may include storage for objects, each object including data associated with a key. A host interface layer may receive requests to read data associated with a key from the storage, to write data associated with a key to the storage, and a boot request to get boot data from the storage. A boot request processor may process the boot request using the storage.

A Key-Value (KV) storage device is disclosed. The KV storage device may include storage for objects, each object including data associated with a key. A host interface layer may receive requests to read data associated with a key from the storage, to write data associated with a key to the storage, and a boot request to get boot data from the storage. A boot request processor may process the boot request using the storage.

A server includes a data cache for storing data objects requested by users logged in under different user roles. Different user roles may have different permissions to access individual fields within a data object. When a cache miss occurs, the cache may begin loading portions of a requested data object from various data sources. Instead of waiting for the entire object to load to change the object state to “valid,” the cache may incrementally update the state through various levels of validity based on the user role of the request. When a portion of the data object used by a low-level user role is received, the object state can be upgraded to be valid for that user role while data for higher-level user roles continues to load. The portion of the data object can then be sent to the low-level user roles without waiting for the rest of the data object to load.

A server includes a data cache for storing data objects requested by users logged in under different user roles. Different user roles may have different permissions to access individual fields within a data object. When a cache miss occurs, the cache may begin loading portions of a requested data object from various data sources. Instead of waiting for the entire object to load to change the object state to “valid,” the cache may incrementally update the state through various levels of validity based on the user role of the request. When a portion of the data object used by a low-level user role is received, the object state can be upgraded to be valid for that user role while data for higher-level user roles continues to load. The portion of the data object can then be sent to the low-level user roles without waiting for the rest of the data object to load.

Systems and methods are provided to perform fine-grained memory accesses using a memory controller. The memory controller can access elements stored in memory across multiple dimensions of a matrix. The memory controller can perform accesses to non-contiguous memory locations by skipping zero or more elements across any dimension of the matrix.

A method begins by a storage unit of a dispersed storage network (DSN) receiving access requests which include a logical DSN address and a storage function. The method continues with a first processing module of the storage unit performing logical to physical address conversions of logical DSN addresses of the access requests to physical addresses of a plurality of main memories. For a first access request of the access requests, the method continues with the first processing module identifying a first main memory based on the physical address resulting from the physical address conversion. The method continues with the first processing module identifying a first processing thread of a plurality of processing threads based on allocation of the plurality of processing threads to the plurality of main memories. The method continues with the first processing thread executing tasks of the first access request to fulfill the first access request.