A system for data communications, comprising an upstream component configured to select an in-band peripheral component interconnect express (PCIe) equalization procedure or an out-of-band PCIe equalization procedure and a downstream component configured to respond to the selected one of the in-band PCIe equalization procedure or the out-of-band PCIe equalization procedure to enable PCIe communications with the upstream component.

One embodiment facilitates a storage system, which comprises a backplane and a plurality of storage medium cards coupled to the backplane. The backplane is coupled to a host via a first interface, and the backplane comprises global management circuitry coupled to a plurality of groups of components and configured to process an input/output (I/O) request and manage a mapping table. A respective group of components includes: first circuitry configured to perform first computing operations; and second circuitry configured to perform second computing operations. A respective storage medium card is allowed to operate without a controller residing on the storage medium card. Data associated with the I/O request is processed by the global management circuitry and further processed by first circuitry and second circuitry associated with a storage medium card selected for executing the I/O request.

A processing device can determine a configuration parameter to be used in an error correction code (ECC) operation. The configuration parameter is based on a memory type of a memory component that is associated with a controller. Data can be received from a host system. The processing device can generate a code word for the data by using the ECC operation that is based on the configuration parameter. The code word can be sent to a sequencer that is external to the controller.

Provided are integrated circuit devices and methods for operating integrated circuit devices. In various examples, an integrated circuit device can be operable to determine, at a point in time during operation of the integrated circuit device, to generate a notification. The notification can include a type and a timestamp indicating the point in time. The notification can also include information about an internal status of the integrated circuit at the point in time. The device can further selectin a queue from a plurality of queues in a processor memory of the computing system that includes the integrated circuit. The device can further generate a write transaction including the notification, where the write transaction is addressed to the queue. The device can further output the write transaction using a communication interface of the device.

Systems and methods for inter-kernel communication using one or more semiconductor devices. The semi-conductor devices include a kernel. The kernel may be in an inactive state unless performing an operation. One kernel of a first device may monitor data for an event. Once an event has occurred, the kernel sends an indication to a first inter-kernel communication circuitry. The inter-kernel communication circuitry determines an activation function of a plurality of activation functions is to be generated, generates the activation function, and transmits the activation function to a second kernel of a second device to waken and perform a function using a peer-to-peer connection.

In example implementations, an apparatus for detecting hardware components is provided. The apparatus includes a multipurpose integrated circuit comprising an input pin, a hardware component coupled to the input pin and a two-way communication bus coupled to the multipurpose integrated circuit. The multipurpose integrated circuit is to receive an interrogation signal from a processor for the hardware component coupled to the pin via the two-way communication bus. A response signal that indicates that the hardware component is detected on the pin is generated in response to the interrogation signal. The response signal is then transmitted to the processor over the two-way communication bus.

Methods and systems for an advanced initialization bus (AIB) are presented. In an aspect, an AIB master sends, to an AIB slave, a serial clock over a first signal line, and performs a read operation with the AIB slave. Performing the read operation comprises sending a read command to the AIB slave via a bus comprising at least one bidirectional input/output (I/O) channel, each I/O channel having its own respective signal line, sending a read address to the AIB slave via the bus, receiving a copy of the serial clock from the AIB slave over a second signal line, and latching read data provided by the AIB slave via the bus into a read buffer using the copy of the serial clock as a data strobe. Thus, the AIB master latches the read data provided by the AIB slave using a read strobe also provided by the AIB slave.

A USB security gateway device is integrated within a host computer. The USB security gateway device is used for protecting a USB port of a host computer against interaction with unauthorized USB device. The USB security gateway device qualifies any USB peripheral device before it allows it to interact with the host device. Qualification parameters are stored in the USB security gateway device and are reprogrammable.

Examples include techniques for coalescing doorbells in a request message. Example techniques include gathering doorbells to access a device. The gathered are combined in a cache line structure and the cache line structure is written to a cache or buffer for a central processing unit in a single write operation.

An integrated circuit includes technology for generating input/output (I/O) latency metrics. The integrated circuit includes a real-time clock (RTC), a read measurement register, and a read latency measurement module. The read latency measurement module includes control logic to perform operations comprising (a) in response to receipt of read responses that complete read requests associated with an I/O device, automatically calculating read latencies for the completed read requests, based at least in part on time measurements from the RTC for initiation and completion of the read requests; (b) automatically calculating an average read latency for the completed read requests, based at least in part on the calculated read latencies for the completed read requests; and (c) automatically updating the read measurement register to record the average read latency for the completed read requests. Other embodiments are described and claimed.