A memory device includes a memory controller to transmit or receive input/output (I/O) data via an I/O signal, as well as transmit command data, address data, or parameter data via another signal in parallel with transmitting or receiving the I/O data. The memory device also includes a memory module communicably coupled to the memory controller. The memory module receives the command data, address data, or parameter data from the memory controller to perform an operation.

SONiC (Software for Open Networking in the Cloud) is instantiated in a chassis-based networking switch device to enable control plane functionality for the line cards and backplane. The SONiC platform may be configured with a routing table and BGP (border gateway protocol) to provide routing capabilities for the application-specific integrated circuits (ASICs) operating on each respective line card. Ethernet ports are utilized within the chassis to enable the utilization of standardized networking protocols, such as protocols on the data link layer (layer 2) within the OSI (Open Systems Interconnection) model. The implementation of SONiC and standardized networking techniques creates a simplified and more proficient routing system in the chassis framework.

An integrated circuit includes technology for generating input/output (I/O) latency metrics. The integrated circuit includes a real-time clock (RTC), a read measurement register, and a read latency measurement module. The read latency measurement module includes control logic to perform operations comprising (a) in response to receipt of read responses that complete read requests associated with an I/O device, automatically calculating read latencies for the completed read requests, based at least in part on time measurements from the RTC for initiation and completion of the read requests; (b) automatically calculating an average read latency for the completed read requests, based at least in part on the calculated read latencies for the completed read requests; and (c) automatically updating the read measurement register to record the average read latency for the completed read requests. Other embodiments are described and claimed.

Techniques for non-disruptive upgrade of a storage appliance may include: restarting a first portion of nodes running a target software version while also running a current software version on a second portion of the nodes, wherein the non-disruptive upgrade is performed to upgrade the nodes of the storage appliance from the current software version to the target software version; performing I/O forwarding where I/Os from the host initiators are serviced using the second portion of the nodes and not serviced using the first portion of the nodes; and determining, in accordance with host initiator login information, whether to continue with the non-disruptive upgrade of the nodes to the target software version. Such techniques may be used, for example, to avoid data unavailability for one or more hosts using the host initiator login information.

An illustrative embodiment disclosed is a circuit including an edge-triggered flip-flop having a first input port, a first clock port, and a first output port. The edge-triggered flip-flop receives, at the first clock port, a strobe having a first edge and a second edge. The edge-triggered flip-flop receives, at the first input port, a control byte time-aligned with the first edge and a data byte time-aligned with the second edge. The edge-triggered flip-flop passes, to the first output port, the control byte based on the first edge and the data byte based on the second edge. The circuit includes an inputs/outputs (I/O) decoder coupled to the first output port. The I/O decoder sends the control byte to microcontroller and sends the data byte to memory cells.

A method for encoding a data value to be transmitted on an SPI serial bus includes an operation to modify a status register of a memory, at least at one chosen time instant, as a function of all or part of the data value to be transmitted.

In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

A data management method includes allocating a buffer for an application based on request information associated with data requested by the application, storing sensor data corresponding to the request information in the buffer, and transferring the sensor data stored in the buffer to the application.

An information processing apparatus includes an interface switching circuit including a first hardware interface to which a first device part is coupled; and a first processor including a second hardware interface, wherein the interface switching circuit is configured to block, when hot-removal of the first device part is detected, a signal path between the first hardware interface and the second hardware interface, and cancel, when diagnosis for a second device part newly hot-inserted in the first hardware interface is completed, the blocking of the signal path in response to a result of the diagnosis, and the first processor is configured to detect presence of the second device part from that the first processor transits from a non-responsive state to a responsible state, and execute an initialization process for the second device part.

One embodiment facilitates a storage system, which comprises a backplane and a plurality of storage medium cards coupled to the backplane. The backplane is coupled to a host via a first interface, and the backplane comprises global management circuitry coupled to a plurality of groups of components and configured to process an input/output (I/O) request and manage a mapping table. A respective group of components includes: first circuitry configured to perform first computing operations; and second circuitry configured to perform second computing operations. A respective storage medium card is allowed to operate without a controller residing on the storage medium card. Data associated with the I/O request is processed by the global management circuitry and further processed by first circuitry and second circuitry associated with a storage medium card selected for executing the I/O request.