According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Devices, systems, and methods for selectively pairing an upstream facing USB port device (UFP device) and a downstream facing USB port device (DFP device) over a network are disclosed. A controller device sends pairing commands to a selected UFP device and a selected DFP device, which then establish a connection with each other over a network. The controller device may subsequently cause the UFP device and/or the DFP device to remove the existing pairing and to instead pair with a different UFP device or DFP device. A pairing between a UFP device and a DFP device allows a host device coupled to the UFP device and a USB device coupled to the DFP device to communicate via a USB-compatible protocol.

A peripheral device controlling device according to an embodiment of the inventive concept includes a command queue for storing at least one Device to Device (D2D) command for data communication between a first peripheral device and a second peripheral device, a command parser for obtaining information related to the data communication from the at least one D2D command, and an orchestrator for controlling at least one of the first peripheral device and the second peripheral device to transfer data from the first peripheral device to the second peripheral device based on the acquired information.

An electronic apparatus and a method of extending peripheral devices are provided. The electronic apparatus includes: a controller; and a plurality of peripheral devices electrically connected to the controller, wherein the plurality of peripheral devices include a plurality of video graphics array display cards, wherein in an initialization phase of the electronic apparatus, the controller allocates input/output resources to a first portion of the video graphics array display cards and does not allocate the input/output resources to a second portion of the video graphics array display cards, wherein the first portion of the video graphics array display cards allocated with the input/output resources is used to display an image in the initialization phase.

A dynamic environment (e.g., an automated industrial process) has multiple conditions in response to which corresponding actions are required, and comprises various equipment, control device(s) to control the equipment, and one or more sensors to generate input signal(s) representing a monitored condition of the environment. A control system for the environment comprises a master processor and one or more co-processors, wherein the master processor configures a given co-processor to evaluate only a first subset of conditions expected to occur in the environment within a specified time period (e.g., less than a response time of the master processor), and to provide first control information representing an action to be taken if a particular condition of the first subset is satisfied. The co-processor receives the input signal(s) representing the monitored condition, processes the input signal(s) so as to determine if the particular condition of the first subset is satisfied, and provides the first control information to the control devices so as to control the equipment. Exemplary applications include dynamic environments in which machine vision techniques and/or equipment are employed.

In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

A computer program product may include storage media embodying program instructions executable by a baseboard management controller (BMC) within a compute node to: receive a request to install a central processing unit (CPU) in the compute node; identify a current hardware configuration of the compute node; identify a plurality of available locations within the compute node that are compatible with installation of the CPU; calculate, for each of the identified plurality of available locations, a predicted performance score for the CPU on the basis that the CPU were to be installed in the available location, wherein the predicted performance scores are calculated in response to receiving the request; select a location from among the plurality of available locations that is associated with the greatest performance score for the CPU; and generate user output indicating the selected location where the CPU should be installed.

An electronic apparatus includes a first processor and a second processor. The first processor includes a detection unit to detect output of an internal-reset occurrence signal from the second processor, and an identification unit to identify, as a source of the internal reset, the second processor in response to the internal-reset occurrence signal and an input of an identification signal from the second processor. The second processor includes an internal reset unit to internally reset the second processor in response to a malfunction of the second processor, a reset occurrence signal output unit to output the internal-reset occurrence signal in response to occurrence of the internal reset of the second processor, and an identification signal output unit to output, to the first processor, the identification signal indicating the source of the internal reset, in response to the occurrence of the internal reset of the second processor.

Described is a method and apparatus for application migration between a dockable device and a docking station in a seamless manner. The dockable device includes a processor and the docking station includes a high-performance processor. The method includes determining a docking state of a dockable device while at least an application is running. Application migration from the dockable device to a docking station is initiated when the dockable device is moving to a docked state. Application migration from the docking station to the dockable device is initiated when the dockable device is moving to an undocked state. The application continues to run during the application migration from the dockable device to the docking station or during the application migration from the docking station to the dockable device.

In example implementations, an apparatus for detecting hardware components is provided. The apparatus includes a multipurpose integrated circuit comprising an input pin, a hardware component coupled to the input pin and a two-way communication bus coupled to the multipurpose integrated circuit. The multipurpose integrated circuit is to receive an interrogation signal from a processor for the hardware component coupled to the pin via the two-way communication bus. A response signal that indicates that the hardware component is detected on the pin is generated in response to the interrogation signal. The response signal is then transmitted to the processor over the two-way communication bus.