G06F13/126

PROVIDING BANDWIDTH EXPANSION FOR A MEMORY SUB-SYSTEM INCLUDING A SEQUENCER SEPARATE FROM A CONTROLLER
20210286665 · 2021-09-16 ·

A processing device can determine a configuration parameter based on a memory type of a memory component that is managed by a memory system controller. The processing device can receive data from a host system. The processing device can generate, by performing a memory operation using the configuration parameter, an instruction based on the data. The processing device can identify a sequencer of a plurality of sequencers that are collocated, within a single package external to the memory system controller, wherein each sequencer of the plurality of sequencers interfaces with a respective memory component. The processing device can send the instruction to the sequencer.

MULTIPLE PROCESSOR COMPUTING DEVICE WITH CONFIGURABLE ELECTRICAL CONNECTIVITY TO PERIPHERALS

A computing device, comprising at least one peripheral computing component, electrically connected to each of a plurality of hardware processors; wherein at least one of the plurality of hardware processors is adapted to executing a code for: configuring the at least one peripheral computing component to access at least one first memory location in a first memory component electrically coupled with a first hardware processor of the plurality of hardware processors via a first electrical connection between the peripheral computing component and the first hardware processor; and configuring the at least one peripheral computing component to access at least one second memory location in a second memory component electrically coupled with a second hardware processor of the plurality of hardware processors via a second electrical connection between the peripheral computing component and the second hardware processor; and wherein the first hardware processor is not the second hardware processor.

SHARED PERIPHERAL DEVICES
20210248091 · 2021-08-12 ·

A peripheral device of a computing device may include a processor; a sharing module to, upon execution of the processor, allow the peripheral device to be shared with an external computing device over a network; and a communication module to, upon execution of the processor: provide data from the peripheral device to a peripheral device hub module of a computing device; and provide communication by the peripheral device with the external computing device.

ELECTRONIC APPARATUS AND METHOD
20210279071 · 2021-09-09 ·

According to one embodiment, an electronic apparatus includes a connection unit configured to be capable of being connected to a host device, a storage unit configured to store device classes of a plurality of types, a processing unit configured to execute processing for establishing communication with the host device connected to the connection unit by selectively using one device class from among the device classes stored in the storage unit, and a processing control unit configured to change the device class to be used for the processing by the processing unit if a message appropriate for the selected device class is not transmitted from the host device.

STORAGE DEVICE AND A STORAGE SYSTEM INCLUDING THE SAME
20210191883 · 2021-06-24 ·

A storage device including: a bridge board to receive a first command; an authenticator to receive user information; and a memory device to receive the first command from the bridge board, the memory device includes a memory controller which determines a status of the memory device, provides status information including the determined status of the memory device to the bridge board, determines the status of the memory device as an unlocked status or a locked status, the bridge board includes a transceiver which communicates with the host through an interface, a register which stores interface information, and a bridge board controller which generates a first response to the first command in a format corresponding to the interface using the interface information, and provides the first response to a host, the first response includes a status bit which inhibits or allows a write operation with respect to the memory device.

SECURE AND POWER EFFICIENT AUDIO DATA PROCESSING

Devices, methods, and systems for secure communications on a computing device. A host operating system (OS) runs on a host processor in communication with a host memory. A secure OS runs on a coprocessor in communication with a secure memory. The coprocessor receives information from an external device over a secure peer-to-peer (P2P) connection. The secure P2P connection is managed by the secure OS and is not accessible by the host OS.

SEQUENCER CHAINING CIRCUITRY
20210200693 · 2021-07-01 ·

A system can include a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto. The system can include chaining circuitry coupled to the plurality of sequencers. The chaining circuitry can comprise logic to: responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; and responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.

Methods, apparatus, and systems for monitoring and/or controlling dynamic environments

A dynamic environment (e.g., an automated industrial process) has multiple conditions in response to which corresponding actions are required, and comprises various equipment, control device(s) to control the equipment, and one or more sensors to generate input signal(s) representing a monitored condition of the environment. A control system for the environment comprises a master processor and one or more co-processors, wherein the master processor configures a given co-processor to evaluate only a first subset of conditions expected to occur in the environment within a specified time period (e.g., less than a response time of the master processor), and to provide first control information representing an action to be taken if a particular condition of the first subset is satisfied. The co-processor receives the input signal(s) representing the monitored condition, processes the input signal(s) so as to determine if the particular condition of the first subset is satisfied, and provides the first control information to the control devices so as to control the equipment. Exemplary applications include dynamic environments in which machine vision techniques and/or equipment are employed.

Massively parallel hierarchical control system and method

An electronic control system is disclosed for controlling individually controllable elements of an external component. In one embodiment the system may include a state translator subsystem for receiving a state command from an external subsystem. The state translator subsystem may have at least one module for processing the state command and generating operational commands for controlling the elements to achieve a desired state or condition. A programmable calibration command translation layer (PCCTL) subsystem may be included which receives and uses the operational commands to generate granular level commands for controlling the elements. A feedback control layer subsystem may be included which applies the granular level commands to the elements, and further modifies the granular level commands as needed to control the elements in closed loop fashion.

Distributed sonic fabric chassis

SONiC (Software for Open Networking in the Cloud) is instantiated in a chassis-based networking switch device to enable control plane functionality for the line cards and backplane. The SONiC platform may be configured with a routing table and BGP (border gateway protocol) to provide routing capabilities for the application-specific integrated circuits (ASICs) operating on each respective line card. Ethernet ports are utilized within the chassis to enable the utilization of standardized networking protocols, such as protocols on the data link layer (layer 2) within the OSI (Open Systems Interconnection) model. The implementation of SONiC and standardized networking techniques creates a simplified and more proficient routing system in the chassis framework.