Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is implemented with each send block associated with a respective FIFO slot. In response to receiving packet data written to the send blocks and detecting the data in those send blocks has egressed from a send context, corresponding freed FIFO slots are detected, and a lowest slot for which credit return indicia has not be returned is determined. The highest slot in a sequence of freed slots from the lowest slot is then determined, and corresponding credit return indicia is returned. In one embodiment an absolute credit return count is implemented for each send context, with an associated absolute credit sent count tracked via software that writes to the PIO send memory, with the two absolute credit counts used for flow control.

Communication traffic processing architectures and methods are disclosed. Processing load on main Central Processing Units (CPUs) can be alleviated by offloading data processing tasks to separate hardware. In one implementation, a processing architecture includes a main processor configured to execute a first portion of a driver software to perform protocol control and management task associated with control or management packets in a packet-based protocol according to which packets are received from a device, an offload processor configured to execute a second portion of the driver software to perform data processing task for data packets received according to the packet-based protocol, an interface to enable communication with the device, and an interconnect coupled to the main processor, to the offload subsystem, and to the interface.

Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals over a serial communication link A method performed at a transmitting device coupled to a communication link includes encoding virtual GPIO signals or messages into a data packet, determining a maximum latency requirement for transmitting the data packet over the communication link, providing a command code header indicating a packet type to be used for transmitting the data packet over the communication link, and transmitting the command code header and the data packet over the communication link in a packet selected to satisfy the maximum latency requirement. A protocol for transmitting the data packet may be determined based on the maximum latency requirement and one or more attributes of protocols available for use on the communication link. In one example, the communication link includes a serial bus and the available protocols include I2C, I3C, and/or RFFE protocols.

Technology related to broadcast packet direct memory access (DMA) operations is disclosed. When a network interface controller (NIC) connected to a host computer receives a broadcast packet, it can transmit a request to an agent process running on the host computer for a plurality of destination buffers. In some embodiments, the request to the agent comprises all or part of the packet, or metadata about the packet. In such embodiments, the agent can use the contents of the request to identify services that should receive the packet. Alternatively, the NIC can identify the destination services and can transmit identifiers for the destination services to the agent. The agent can transmit requests for memory buffers to the services and can receive memory location identifiers in response. The agent can transmit the identifiers to the NIC, which can perform multiple DMA operations to write the broadcast packet to the identified memory locations.

The Wireless Small Form-factor Pluggable (SFP) Interface Module is an extraordinary invention poised to redefine the telecommunications industry. This cutting-edge patent introduces an unparalleled solution to the intricate challenges of data center cabling infrastructure. The wireless SFP module, a revolutionary technology, promises swifter, more secure, and more efficient data transmissions. This next-generation solution, leveraging a sophisticated wireless transceiver, facilitates wireless data transmission and reception, thereby curtailing downtime and augmenting network efficiency. The wireless SFP module is not merely a technological advancement; it's a leap into the future of data center infrastructure. The impact of this patent transcends the confines of telecommunications, promising extensive industry-wide ramifications, thereby heralding a new era in digital communication.

A metadata processing method includes a network interface card in a storage device that receives an input/output (I/O) request, where the I/O request includes a data read request or a data write request; the network interface card executes a metadata processing task corresponding to the I/O request; and when determining that the metadata processing task fails to be executed, the network interface card requests a CPU in the storage device to execute the metadata processing task.

An integrated circuit device for receiving packets. The integrated circuit device includes a programmable partitionable counter that includes a first counter partition for counting a number of the packets, and a second counter partition for counting bytes of the packets. The first counter partition and the second counter partition are configured to be incremented by a single command from the packet processor.

An electronic device is provided. The electronic device includes a transceiver that communicates with an external electronic device and at least one processor electrically connected with the transceiver. The processor is configured to obtain context information about an operation being performed at the electronic device, to generate identification information about a recommended operation associated with the operation being performed, based on the context information about the operation being performed and to send the identification information about the recommended operation to the external electronic device by using the transceiver.

A system and method is provided for generating network timeouts by utilizing intentionally delayed message transmissions sent internal to a network controller. For example, according to this system and method a network controller transmits a data message externally over a network and the data message invokes a response network message. The network controller also transmits a timeout message corresponding to the data message; however, the timeout message is intentionally delayed for a predetermined duration of time prior to being internally transmitted. controller host device receives at least one of the response message and the timeout message and determines which is received first. If the timeout message is received, a request associated with the transmitted data message is treated as having timed out.

Embodiments of the technology can provide steering of one or more I/O resources to compute subsystems on a system-on chip (SoC). The SoC may include a first I/O subsystem comprising a plurality of first I/O resources and a second I/O subsystem comprising a plurality of second I/O resources. A steering engine may steer at least one of the first I/O resources to either a network compute subsystem or to a server compute subsystem and may steer at least one of the second I/O resources to either the network compute subsystem or to the server compute subsystem.