Remote direct memory access (RDMA) enables access to a memory resource on a computing device without involving the device's CPU (central processing unit). Data packets traversing a NIC (network interface controller/card) on a server in a network are efficiently captured by adapting an ASIC (application-specific circuit) in a programmable TOR (top of rack) switch to modify headers of incoming data packets to indicate to the NIC that the packets are RDMA packets. Such modification enables the packets to be written directly to the server memory while bypassing the server's CPU which can typically act as a bottleneck when attempting full packet capture.

A network element including buffer address control circuitry for reading a given entry from a queue in a memory of a device external to the network element, the queue having at least a first entry and a last entry, the given entry including a destination address in the memory, output circuitry for writing data included in a packet received from external to the network element to the destination address in the memory in accordance with the given entry, and next entry assignment circuitry for assigning a next entry by: when the given entry is other than the last entry in the first queue, assigning the next entry to be an entry in the first queue after the given entry, and when the given entry is the last entry in the first queue, assigning the next entry to be the first entry in the first queue. Related apparatus and methods are also described.

In one embodiment, a direct memory access (DMA) controller within a host device obtains a packet to be processed by the host device, where the host device comprises a host processor, a network interface controller (NIC), and a co-processor of the NIC, and where the co-processor is configured to perform one or more specific packet processing operations. The DMA controller may then detect a DMA descriptor of the packet, and can determine, according to the DMA descriptor, how the packet is to be moved for processing within the host device. As such, the DMA controller may then move the packet, based on the determining, to one of either a host main memory, a NIC memory, or a co-processor memory of the host device.

A smart network interface controller (NIC) implemented using a stacked die configuration is provided. The NIC may include user-customizable networking circuits formed in a top programmable die and primitive network function blocks formed in a bottom application-specific integrated circuit (ASIC) die. The top programmable die may provide a flexible packet processing pipeline to facilitate efficient control and data communication between the user-customizable networking circuits and the primitive network function blocks. The bottom ASIC die may also include an array of memory blocks operable as lookup tables and intermediate buffers for other network processing circuitry in the NIC. A NIC configured in this way provides both performance, power, and area benefits and superior customer configurability.

In one example, at least one peripheral interconnect switch obtains, from a first endpoint device, a message initiating a direct memory access data transfer between the first endpoint device and a second endpoint device. The message indicates an address assigned to the second endpoint device by a host device as a destination of the message. Based on the address assigned to the second endpoint device by the host device, the at least one peripheral interconnect switch identifies an address assigned to the second endpoint device by the at least one peripheral interconnect switch. In response to identifying the address assigned to the second endpoint device by the at least one peripheral interconnect switch, the at least one peripheral interconnect switch provides the message to the second endpoint device.

Examples described herein relate to executing a poller to poll for received communications over multiple transport layer protocols from a connection to identify a received communication from one of the multiple transport layer protocols and identify a second received communication from a different one of the multiple transport layer protocols. A change to the different one of the multiple transport layer protocols occurs in response to failure of the one of the multiple transport layer protocols or slow transport rate using the one of the multiple transport layer protocols. In some examples, the poller is executed in user space and transport layer protocol processing of the received communication and second received communication occur in kernel space.

Devices for coordinating or establishing a direct memory access for a network interface card to a graphics processing unit, and for a network interface card to access a graphics processing unit via a direct memory access are disclosed. For example, a central processing unit may request a graphics processing unit to allocate a memory buffer of the graphics processing unit for a direct memory access by a network interface card and receive from the graphics processing unit a first confirmation of an allocation of the memory buffer. The central processing unit may further transmit to the network interface card a first notification of the allocation of the memory buffer of the graphics processing unit, poll the network interface card to determine when a packet is received by the network interface card, and transmit a second notification to the graphics processing unit that the packet is written to the memory buffer.

Aspects of peripheral device sharing for virtual machines are described. In some aspects, a virtual machine requires access to a peripheral device. The virtual machine is executed in a first host computing system. A table is accessed, and includes a list of peripheral devices, an indication that the peripheral device is connected to a second host computing system, a bandwidth requirement of the peripheral device, and a network bandwidth allocated to the virtual machine. The virtual machine is provided with access to the peripheral device based on a comparison between the bandwidth requirement of the peripheral device, and a threshold percentage of the network bandwidth allocated to the virtual machine.

An electronic device having a display, radio frequency (RF) circuitry, and one or more input devices, displays a first user interface on the display. While displaying the first user interface, the electronic device detects a pairing request to pair a first peripheral with the electronic device. In response to detecting the pairing request, the electronic device pairs the first peripheral with the electronic device, and after the first peripheral is paired with the electronic device, the electronic device concurrently displays status information of the first peripheral and a second peripheral, wherein the first peripheral is coupled to the second peripheral, or the first peripheral and second peripheral are both coupled to a third peripheral.

A buffer (32) for temporarily storing a packet is installed in a packet order control circuit (12H). A comparison circuit (31) compares the packet ID of an input packet with a next-selection ID indicating the packet ID of a packet to be selected next in accordance with an order. If the comparison result indicates that the packet ID and the next-selection ID do not match, a control circuit (36) stores the input packet in a storage position corresponding to the packet ID. If the packet ID and the next-selection ID match, the control circuit (36) selects the input packet as a target of a transfer process without storing the packet in the buffer (32). If the next-selection ID matches the packet ID of a packet stored in the buffer (32), the control circuit (36) selects the packet as a target of the transfer process. This guarantees the packet processing order with few memory resources.