A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

A method includes receiving a write request to a write queue of a host having the write queue and a read queue; initiating a write queue timer upon receiving the write request to the write queue of the host, wherein the write queue timer has a write queue timer expiry threshold value; and executing one or more write requests when the write queue timer reaches the write queue timer expiry threshold value.

Methods and apparatus for starvation mitigation for associative cache designs. A memory controller employs an associative cache to cache physical page addresses and logic to monitor a level of cache contention. When the contention reaches a critical level where QoS can’t be guaranteed, a backpressure mechanism is triggered by cache contention mitigation logic to prevent new memory access commands from a host from entering a command pipeline. The mitigation logic maintains the backpressure until the monitoring logic indicates that the contention has resolved. The levels of contention that triggers and releases the backpressure may be set using configurable control registers. A starvation counter is incremented when a cache slot cannot be allocated for a command and decremented when a replayed command is allocated a slot. A starvation count is evaluated to determine when backpressure should be triggered and released.

A memory setting method and apparatus the method including obtaining, by a processor that is in a non-uniform memory access architecture (NUMA) system and that has at least two memories, performance of the at least two memories upon the processor starting, and setting, based on the performance of the at least two memories, at least one of the at least two memories as a local memory, and setting, based on the performance, at least one of the at least two memories as a remote memory, where performance of the local memory is better than performance of the remote memory.

A memory controller includes a command queue that receives and stores decoded memory commands and information related thereto including information indicating a type, a priority, an age, and a region of a memory system for a corresponding decoded memory command, and an arbiter coupled to the command queue and picks selected decoded memory commands among the decoded memory commands from the command queue for dispatch to the memory system by comparing the priority and the age for decoded memory commands having a first type. The arbiter detects when the command queue receives a decoded memory command of a second type opposite to said first type that accesses a first memory region of the memory system, and in response performs at least one pre-work action that reduces a latency of the decoded memory command of the second type.

An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.

A technique is described for performing a maintenance operation within an apparatus that is used to control access to a memory device. The apparatus has a storage device for storing access requests to be issued to the memory device, and maintenance circuitry for performing a maintenance operation on storage elements provided within the storage device. Memory access execution circuitry is used to issue to a physical layer interface access requests selected from the storage device, for onward propagation from the physical layer interface to the memory device. Control circuitry is responsive to a training event to initiate a training operation of the physical layer interface. In addition, the control circuitry is further responsive to the training event to trigger performance of the maintenance operation by the maintenance circuitry whilst the training operation is being performed. During the training operation, none of the pending access requests will be issued to the memory device, and accordingly by performing the maintenance operation during this period, the potential impact that the performance of the maintenance operation could have had on the handling of the access requests is avoided.

The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

Embodiments are generally directed apparatuses, methods, techniques and so forth to select two or more processing units of the plurality of processing units to process a workload, and configure a circuit switch to link the two or more processing units to process the workload, the two or more processing units each linked to each other via paths of communication and the circuit switch.

A method for configuring a transfer of signals associated with an iterative and synchronized, time-based data acquisition (DAQ) operation between at least one input device and at least one output device is disclosed herein. The method includes requesting and receiving signal data samples (SDSs) from the at least one input device. A series of the SDSs are mapped to a buffer. The time indicators of SDSs are compared to confirm that SDSs are incrementally-next in time relative one another. A missing signal data sample is retransmitted if necessary. The series of SDSs is remapped in the buffer as necessary to arrange the series in time sequence. The method also includes transmitting in real time at least a portion of the present signal data sample to an output device prior to receiving the missing signal data sample.