A serial interface is provided with a finite state machine configured to compare a current state for a plurality of signals to a previous state to determine whether to transmit a frame including the plurality of signals or to transmit a frame that includes only a bit position of a changed one of the signals.

A data processing method, including dividing a to-be-processed data block into multiple data subblocks, where a quantity of the multiple data subblocks is less than or equal to a quantity of banks Banks of a memory, and performing an access operation on a bank corresponding to each data subblock of the to-be-processed block, where different data subblocks of the block are corresponding to different Banks of the memory. In an embodiment of the present disclosure, a processor maps different data subblocks of a to-be-processed Block to different Banks, so that a quantity of inter-page access operations on a same Block may be reduced, thereby improving memory access efficiency when two contiguous memory access operations access different pages of a same bank.

In accordance with an embodiment of the invention, higher-speed outgoing data paths are used to transmit oversampled data signals, and corresponding slower-speed return data paths are used to receive return data signals. A channel-bonding control circuit measures the skew between the returned data signals and generates bit-slip and/or word-slip control signals to compensate for the skew. Transmission bit-slip (or, alternatively, clock-slip) circuits slip integer numbers of bits based on the bit-slip control signals. Bypass registers (or, alternatively, FIFO write or read enable signals) may be used to slip a whole word when the integer number of bits to slip is greater or equal to the parallel width of a lane. Various other aspects, features, and embodiments are also disclosed.

Systems and methods are disclosed including a first memory device, a second memory device coupled to the first memory device, where the second memory device has a lower access latency than the first memory device and acts as a cache for the first memory device. A processing device operatively coupled to the first and second memory devices can track access statistics of segments of data stored at the second memory device, the segments having a first granularity, and determine to update, based on the access statistics, a segment of data stored at the second memory device from the first granularity to a second granularity. The processing device can further retrieve additional data associated with the segment of data from the first memory device and store the additional data at the second memory device to form a new segment having the second granularity.

The present disclosure generally presents a method and apparatus to provide a bounded latency, where a device would report “non-service” of a command at the defined system level timeout or earlier if the device was unable to successfully return the data to the host.

A system includes a synchronizer circuit configured to monitor a first bus coupled between a memory and a first device to determine an occupancy threshold of the memory based on one or more write requests from the first device. The synchronizer circuit monitors a second bus between the memory and a second device to receive a first read transaction of a read request from the second device. The synchronizer circuit determines that the first read transaction is allowed to be sent to the memory based on the occupancy threshold of the memory. In response to the determination, the first read transaction is sent to the memory.

Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

A data processing system includes a plurality of resources suitable for processing data, a host suitable for requesting at least one of the plurality of resources to process the data, a plurality of data paths suitable for transferring the data between the host and the plurality of resources, and an arbiter suitable for dividing the plurality of resources into a plurality of groups, allocating at least one first data path of the plurality of data paths to each of the groups, and rearranging the plurality of groups, based on their respective transmission statuses, by additionally allocating at least one second data path of the plurality of data paths to each of the groups or by moving at least one resource from one of the plurality of groups to another of the plurality of groups.

A generic physical layer providing a unified architecture for interfacing with an external memory device. The physical layer comprises a transmit data path for transmitting a parallel data to the external memory device and a receive data path for receiving a serial data from the external memory device. The generic physical layer is characterized by a receive enable logic for masking strobe of the serial data, wherein the transmit data path and the receive data path each comprising a FIFO circuit, a data rotator and an adjustable-delay logic for delay tuning and a per-bit-deskew for multi-lane support.

The memory sub-systems of the present disclosure discloses a just-in-time (JIT) scheduling system and method. In one embodiment, a system receives a request to perform a memory operation using a hardware resource associated with a memory device. The system identifies a traffic class corresponding to the memory operation. The system determines a number of available quality of service (QoS) credits for the traffic class during a current scheduling time frame. The system determines a number of QoS credits associated with a type of the memory operation. Responsive to determining the number of QoS credits associated with the type of the memory operation is less than the number of available QoS credits, the system submits the memory operation to be processed at a memory device.