Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.

Systems and methods for dynamic and adaptive interrupt coalescing are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device notifies the host device, via an interrupt, of entries on the completion queue. Responsive to receiving the interrupt, the host device access the completion queue to access entries placed by the memory device therein. The host device may take a certain amount of time to service the interrupt resulting in host latency. Given knowledge of the host latency, the memory device time the sending of the interrupt so that, given the host latency, the memory device may post the entry to the completion queue in a timely manner.

Systems, apparatuses, and methods for implementing a primary input/output (PIO) queue for host and guest operating systems (OS's) are disclosed. A system includes a PIO queue, one or more compute units, and a control unit. The PIO queue is able to store work commands for multiple different types of OS's, including host and guest OS's. The control unit is able to dispatch multiple work commands from multiple OS's to execute concurrently on the compute unit(s). This allows for execution of work commands by different OS's without the processing device(s) having to incur the latency of a world switch.

Technology is disclosed for allocating PCIe bus bandwidth to storage commands in a peer-to-peer environment. A non-volatile storage system has a peer-to-peer connection with a host system and a target device, such as a GPU. A memory controller in the storage system monitors latency of PCIe transactions that are performed over a PCIe bus in order to transfer data for NVMe commands. The PCIe transactions may involve direct memory access (DMA) of memory in the host system or target device. There could be a significant difference in transaction latency depending on what memory is being accessed and/or what communication link is used to access the memory. The memory controller allocates bandwidth on a PCIe bus to the NVMe commands based on the latencies of the PCIe transactions. In an aspect, the memory controller groups the PCIe addresses based on the latencies of the PCIe transactions.

A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a plurality of cache read commands requesting first data from the memory array spread across the plurality of memory planes and receives, from the requestor, a cache read context switch command and a snap read command requesting second data from one of the plurality of memory planes of the memory array. Responsive to receiving the cache read context switch command, the control logic suspends processing of the plurality of cache read commands and processes the snap read command to read the second data from the memory array and return the second data to the requestor.

Ensuring the appropriate utilization of system resources using weighted workload based, time-independent scheduling, including: receiving an I/O request associated with an entity; determining whether an amount of system resources required to service the I/O request is greater than an amount of available system resources in a storage system; responsive to determining that the amount of system resources required to service the I/O request is greater than the amount of available system resources in the storage system: queueing the I/O request in an entity-specific queue for the entity; detecting that additional system resources in the storage system have become available; and issuing an I/O request from an entity-specific queue for an entity that has a highest priority, where a priority for each entity is determined based on the amount of I/O requests associated with the entity and a weighted proportion of resources designated for use by the entity.

Ensuring the fair utilization of system resources using workload based, time-independent scheduling, including: determining whether an amount of available system resources in the storage system has reached a predetermined reservation threshold; and responsive to determining that the amount of available system resources in the storage system has reached the predetermined reservation threshold: determining whether one or more entities in the storage system have utilized system resources in excess of their fair share by a predetermined threshold during one or more time-independent periods; and responsive to determining that one or more entities in the storage system have utilized system resources in excess of their fair share by the predetermined threshold during the time-independent period, limiting the one or more entities from issuing additional I/O requests to the storage system.

Systems and methods for adaptive fetch coalescing are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The host device notifies the memory device, via a doorbell update, of commands on the submission queue. Instead of fetching the command responsive to the doorbell update, the memory device may analyze one or more aspects in order to determine whether and how to coalesce fetching of the commands. In this way, the memory device may include the intelligence to coalesce fetching in order to more efficiently fetch the commands from the host device.

A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

An apparatus including a plurality of set arbitration circuits and a die arbitration circuit. The set arbitration circuits may each be configured to receive first commands and second commands and comprise a bank circuit configured to queue bank data in response to client requests and a set arbitration logic configured to queue the second commands in response to the bank data. The die arbitration circuit may be configured to receive the commands from the set arbitration circuits and comprise a die-bank circuit configured to queue die data in response to the client requests and a die arbitration logic configured to queue the second commands in response to the die data. Queuing the bank data and the die data for the second commands may maintain an order of the client requests and prioritize the first commands corresponding to a current controller over the first commands corresponding to a non-current controller.