According to embodiments of the present disclosure, there is provided a data transmission apparatus. The data transmission apparatus includes a plurality of first ports, a plurality of second ports, and a plurality of data channels. The plurality of first ports are coupled to a processing unit. The plurality of second ports are coupled to a plurality of memories. The plurality of data channels are disposed among the first ports and the second ports to form an interleaving network having a plurality of layers, and configured to transmit data among the processing unit and the plurality of memories, such that each layer in the interleaving network includes at least one interleaving sub-network.

A method for accessing a dynamic memory module, the method may include (i) receiving, by a memory controller, a set of access requests for accessing the dynamic memory module; (ii) converting the access requests to a set of commands, wherein the set of commands comprise (a) a first sub-set of commands that are related to a first group of memory banks, and (b) a second sub-set of commands that are related to a second group of memory banks; (iii) scheduling, by a scheduler of the memory controller, an execution of the first sub-set; (iv) scheduling an execution of the second sub-set to be interleaved with the execution of the first sub-set; and (v) executing the set of commands according to the schedule.

A display driver integrated circuit (IC) includes a logic module sequentially issuing read commands including a first read command, a second read command succeeding the first read command, and a third read command succeeding the second read command, and memory modules connected in series with each other. A first memory module is connected to the logic module and is the closest memory module to the logic module. The first memory module receives the read commands, provide the first read command to a first memory of the first memory module, read first image data from the first memory in response to the first read command, and provide the first image data and first remaining read commands among the read commands to a second memory module which is connected to the first memory module and farther than the first memory module from the logic module.

An information processing device include: a memory; and a processor coupled to the memory and configured to: receive an access request directed to an access target and sets the access request in any one of a plurality of pending entries each of which includes latency information; issue a command that corresponds to the access request; control issuance of the command on a basis of the latency information of the any one of the pending entries; set a value that indicates latency for the access request in the latency information of the any one of the pending entries; and subtract a predetermined value from the latency information of the any one of the pending entries for each unit of time.

A memory controller includes a command queue that receives and stores decoded memory commands and information related thereto including information indicating a type, a priority, an age, and a region of a memory system for a corresponding decoded memory command, and an arbiter coupled to the command queue and picks selected decoded memory commands among the decoded memory commands from the command queue for dispatch to the memory system by comparing the priority and the age for decoded memory commands having a first type. The arbiter detects when the command queue receives a decoded memory command of a second type opposite to said first type that accesses a first memory region of the memory system, and in response elevates at least one of the priority and the age of a decoded command of the first type that accesses the first memory region already stored in the command queue.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing data on a memory controller. One of the methods comprises obtaining a first request and a second request to access respective data corresponding to the first and second requests at a first memory device of the plurality of memory devices; and initiating interleaved processing of the respective data; receiving an indication to stop processing requests to access data at the first memory device and to initiate processing requests to access data at a second memory device, determining that the respective data corresponding to the first and second requests have not yet been fully processed at the time of receiving the indication, and in response, storing, in memory accessible to the memory controller, data corresponding to the requests which have not yet been fully processed.

A memory device includes a memory array and a memory controller. The memory array includes a first memory bank, a second memory bank, and a third memory bank. The first memory bank includes a first sub memory bank. The second memory bank includes a second sub memory bank. The memory controller, according to a write command from a host, writes first data from the host to the first memory bank and second data to the second memory bank at the same time, and writes a first Hamming weight of the first data to the third memory bank. The second data is the inverse of the first data.

A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit. The first memory bank includes a memory array divided into a plurality of grains, each grain including a row buffer and input/output (I/O) circuitry. The dual-mode I/O circuit is coupled to the I/O circuitry of each grain in the first memory bank, and operates in a first mode in which commands having a first data width are routed to and fulfilled individually at each grain, and a second mode in which commands having a second data width different from the first data width are fulfilled by at least two of the grains in parallel.

A display driver integrated circuit (IC) includes a logic module sequentially issuing read commands including a first read command, a second read command succeeding the first read command, and a third read command succeeding the second read command, and memory modules connected in series with each other. A first memory module is connected to the logic module and is the closest memory module to the logic module. The first memory module receives the read commands, provide the first read command to a first memory of the first memory module, read first image data from the first memory in response to the first read command, and provide the first image data and first remaining read commands among the read commands to a second memory module which is connected to the first memory module and farther than the first memory module from the logic module.

A display driver integrated circuit (IC) includes a logic module sequentially issuing read commands including a first read command, a second read command succeeding the first read command, and a third read command succeeding the second read command, and memory modules connected in series with each other. A first memory module is connected to the logic module and is the closest memory module to the logic module. The first memory module receives the read commands, provide the first read command to a first memory of the first memory module, read first image data from the first memory in response to the first read command, and provide the first image data and first remaining read commands among the read commands to a second memory module which is connected to the first memory module and farther than the first memory module from the logic module.