A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple applications. For example, the transmitter and/or receiver latency paths of the transceiver can share an interleaver/deinterleaver memory. This allocation can be done based on the data rate, latency, BER, impulse noise protection requirements of the application, data or information being transported over each latency path, or in general any parameter associated with the communications system.

A memory system may include: a memory controller; a plurality of ranks; and a rank shared bus configured to couple the memory controller and the plurality of ranks. Each of the plurality of ranks may include: a plurality of banks; a rank bus coupled to the plurality of banks and configured to selectively transmit data to the rank shared bus or an intermediate buffer and selectively receive data from the rank shared bus or the intermediate buffer; and an intermediate buffer configured to be selectively coupled to the rank bus or the rank shared bus, according to a first signal from the memory controller.

A memory system may include: a memory controller; a plurality of ranks; and a rank shared bus configured to couple the memory controller and the plurality of ranks. Each of the plurality of ranks may include: a plurality of banks; a rank bus coupled to the plurality of banks and configured to selectively transmit data to the rank shared bus or an intermediate buffer and selectively receive data from the rank shared bus or the intermediate buffer; and an intermediate buffer configured to be selectively coupled to the rank bus or the rank shared bus, according to a first signal from the memory controller.

The present disclosure relates to a method, an apparatus, an electronic device and a computer readable storage medium for accessing static random access memories. The method includes: receiving an access request for data associated with the static random access memories; writing a plurality of sections of the data into a plurality of different static random access memories in an interleaved manner in response to the access request being a write request for the data, each of the plurality of sections having its respective predetermined size; and reading the plurality of sections of the data from the plurality of static random access memories in an interleaved manner in response to the access request being a read request for the data, each of the plurality of sections having its respective predetermined size.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing data on a memory controller. One of the methods comprises obtaining a first request and a second request to access respective data corresponding to the first and second requests at a first memory device of the plurality of memory devices; and initiating interleaved processing of the respective data; receiving an indication to stop processing requests to access data at the first memory device and to initiate processing requests to access data at a second memory device, determining that the respective data corresponding to the first and second requests have not yet been fully processed at the time of receiving the indication, and in response, storing, in memory accessible to the memory controller, data corresponding to the requests which have not yet been fully processed.

A memory system includes a plurality of memory dies and a controller coupled with the plurality of memory dies via a plurality of channels. The controller is configured to perform a correlation operation on at least some read requests among a plurality of read requests inputted from an external device so that the plurality of memory dies outputs plural pieces of data corresponding to the plurality of read requests via the plurality of channels in an interleaving way. The controller is configured to determine when to perform the correlation operation based on the number of the plurality of read requests.

Methods, systems, and apparatus, including computer-readable media, are described for interleaving memory requests to accelerate memory accesses at a hardware circuit configured to implement a neural network model. A system generates multiple requests that are processed against a memory of the system. Each request is used to retrieve data from the memory. For each request, the system generates multiple sub-requests based on a respective size of the data to be retrieved using the request. The system generates a sequence of interleaved sub-requests that includes respective sub-requests of a first request interleaved among respective sub-requests of a second request. Based on the sequence of interleaved sub-requests, a module of the system receives respective portions of data accessed from different address locations of the memory. The system processes each of the respective portions of data to generate a neural network inference using the neural network model implemented at the hardware circuit.

A memory system may include a plurality of memory dies configured to store data therein, and a controller coupled to the plurality of memory dies through a plurality of channels, and configured to correlate at least some of a plurality of read requests and transferring the plurality of read requests to the plurality of channels, such that the plurality of read requests are processed in an interleaving way through the plurality of channels, when controlling the plurality of memory dies for the plurality of read requests. The controller may determine whether to perform the correlation operation in response to the number of the plurality of read requests, wherein the plurality of read requests include a read request for an internal operation of the controller and a read request received from a host.

The present invention provides a control method of multiple memory devices, wherein the multiple devices comprise a first memory device and a second memory device, and the control method includes the steps of: determining a first operation timing and a second operation timing according to at least a first command signal that a first memory controller needs to send to the first memory device; controlling the first memory controller to send the first command signal to the first memory device at the first operation timing; and controlling the second memory controller to send the second command signal to the second memory device at the second operation timing.

A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple applications. For example, the transmitter and/or receiver latency paths of the transceiver can share an interleaver/deinterleaver memory. This allocation can be done based on the data rate, latency, BER, impulse noise protection requirements of the application, data or information being transported over each latency path, or in general any parameter associated with the communications system.