A computing system having memory components, including first memory and second memory, wherein the first memory is available to a host system for read and write access over a memory bus during one or more of a first plurality of windows. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, from a driver of the host system, a request regarding a page of data stored in the second memory; responsive to the request, transfer the page from the second memory to a buffer; and write the page from the buffer to the first memory, wherein the page is written to the first memory during at least one of a second plurality of windows corresponding to a refresh timing for the memory bus, and the refresh timing is controlled at the host system.

Techniques of memory inclusivity management are disclosed herein. One example technique includes receiving a request from a core of the CPU to write a block of data corresponding to a first cacheline to a swap buffer at a memory. In response to the request, the method can include retrieving metadata corresponding to the first cacheline that includes a bit encoding a status value indicating whether the memory block at the memory currently contains data of the first cacheline or data corresponding to a second cacheline. The first and second cachelines alternately sharing the swap buffer at the memory. When the decoded status value indicates that the memory block at the first memory currently contains the data corresponding to the first cacheline, an instruction is transmitted to the memory controller to directly write the block of data to the memory block at the first memory.

A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

Provided are a non-volatile dual inline memory module (NVDIMM) supporting a DRAM cache mode and an operation method of the NVDIMM. The NVDIMM includes a DRAM chip, an NVM chip, and a controller that controls the DRAM chip to operate as a cache memory of the NVM chip. The controller sends a read command to the DRAM chip with reference to a cache address of data requested to be written from a host to the NVM chip, and sends a write command to the NVM chip with reference to an address of the data requested to be written at a time point when a read latency (RL) of the DRAM chip and a write latency (WL) of the NVM chip coincide with each other.

Disclosed approaches eliminate involving a bus interface in polling by the host computer system and the peripheral component for events to coordinate direct memory access (DMA) transfers. The host polls main memory for DMA events communicated by the peripheral component, and the peripheral component polls local registers for DMA addresses to initiate DMA transfers. DMA transfers are initiated by the host storing main memory addresses in the local registers of the peripheral component, and DMA events generated by the peripheral component are stored in the main memory.

Disclosed is a method for accessing data from a flash memory. The method comprises a flash memory controller receiving an access command from a host device, according to the access command, the flash memory accessing a plurality of data from the data pages of a plurality of blocks in the flash memory simultaneously and simultaneously temporarily storing the accessed data to the plurality of buffers of the flash memory, and simultaneously temporarily storing the data in the plurality of buffers of the flash memory buffer to the plurality of buffers the flash memory controller.

Embodiments of the present disclosure relate to circular buffers in a neural processor circuit. The neural processor circuit includes multiple neural engine circuits and a data processor circuit coupled to at least one of the neural engine circuits. The at least one neural engine circuit performs at least convolution operations. The data processor circuit includes a circular buffer, and a flow control circuit coupled to the circular buffer. The flow control circuit generates at least one addressing parameter that defines wrapping of data in the circular buffer. The circular buffer controls data flow in the neural processor circuit by storing first data associated with the at least one neural engine circuit so that the first data is wrapped around in the circular buffer. An addressing layout of the first data wrapped around in the circular buffer is defined by the at least one addressing parameter.

The controller is configured to receive commands from a host device through a PCIe bus having a MAC, send data to the host device through the PCIe bus, and execute a function level reset (FLR) command. The controller includes a direct memory access (DMA) unit and either a drain unit or a drain and drop unit coupled between the DMA and the PCIe bus. The units are configured to prevent transactions associated with the FLR command to pass from the DMA to the MAC during execution of the FLR command, where the preventing transactions comprises receiving a request from the DMA, storing the request in a pipe, removing the request from the pipe, and providing a response to the DMA without delivering the request to the MAC. The drain and drop unit is configured to drop a MAC generated response.

A semiconductor device capable of shortening a time required for data transfer and data organizing is provided. The solid state device includes a processor, a memory, an external interface, registers for storing data received by the external interface, a mirror register buffer, a processor, a memory, an external interface, registers, and an internal bus connected to the mirror register buffer. Registers output data to the mirror register buffer without going through the internal bus. Mirror register buffer gives the data input from the registers an address in a mirror register buffer different from the address allocated to the register, and transfers the data to the memory without passing through the internal bus.

A computerized system for efficient interaction between a host, the host having a first operating system, and a second operating system, the system comprising a subsystem on the second operating system which extracts data, directly from a buffer which is local to the host, wherein the system is operative for mapping memory from one bus associated with the first operating system to a different bus, associated with the second operating system and from which different bus the memory is accessed, thereby to emulate a connection between the first and second operating systems by cross-bus memory mapping.