A system, apparatus, and method for testing blocks of a system on a chip (SOC) are described herein. An SOC, in accordance with various embodiments, may include a serial communication interface configured to multiplex, serialize, and/or parallelize signals streams from selected blocks of the SOC to an off-chip test unit through an off-chip serial communication interface. Other embodiments may be described and claimed.

The present disclosure includes apparatuses and methods related to memory module interfaces. A memory module, which may include volatile memory or nonvolatile memory, or both, may be configured to communicate with a host device via one interface and to communicate with another memory module using a different interface. Memory modules may thus be added or removed from a system without impacting a PCB-based bus to the host, and memory modules may communicate with one another without accessing a bus to the host. The host interface may be configured according to one protocol or standard, and other interfaces between memory modules may be configured according to other protocols or standards.

Systems and method for arbitrating requests to a shared memory system for reducing power consumption of memory accesses, comprises determining power modes associated with memory channels of the shared memory system, assigning priorities to the requests based at least in part on the power modes, and scheduling the requests based on the assigned priorities. Latency characteristics and page hit rate are also considered for assigning the priorities.

Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

In one form, a data processing system includes a memory channel having a plurality of ranks, and a data processor. The data processor is coupled to the memory channel and is adapted to access each of the plurality of ranks. In response to detecting a predetermined event, the data processor selects an active rank of the plurality of ranks and places other ranks besides the active rank in a low power state, wherein the other ranks include at least one rank with a pending request at a time of detection of the predetermined event. The data processor subsequently processes a memory access request to the active rank.

Command execution data is received. The command execution data comprises a block address corresponding to an functional component, a register identifier corresponding to a design for testability (DFT) register of the functional component, and command data. The command execution data is converted to a serial command. The serial command is committed to the DFT register of the functional component. A response to the serial command is received. The response is generated by the functional component based on the serial command. The response is converted to command response data and is provided to a testing sub-system.

Systems and methods are disclosed for expanding memory for a system on chip (SoC). A memory card is loaded in an expandable memory socket electrically and is coupled to a system on chip (SoC) via an expansion bus. The memory card comprises a first volatile memory device. In response to detecting the memory card, an expanded virtual memory map is configured. The expanded virtual memory map comprises a first virtual memory space associated the first volatile memory device and a second virtual memory space associated with a second volatile memory device electrically coupled to the SoC via a memory bus. One or more peripheral images associated with the second virtual memory space are relocated to a first portion of the first virtual memory space. A second portion of the first virtual memory space is configured as a block device for performing swap operations associated with the second virtual memory space.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. In a representative embodiment, a system includes an interconnection network, a processor, a host interface, and a configurable circuit cluster. The configurable circuit cluster may include a plurality of configurable circuits arranged in an array; an asynchronous packet network and a synchronous network coupled to each configurable circuit of the array; and a memory interface circuit and a dispatch interface circuit coupled to the asynchronous packet network and to the interconnection network. Each configurable circuit includes instruction or configuration memories for selection of a current data path configuration, a master synchronous network input, and a data path configuration for a next configurable circuit.

A memory system includes: a plurality of memory devices, one of which includes an unrepaired defective memory cell; a control bus that is shared by the plurality of the memory devices; a plurality of data buses assigned to each of the plurality of the memory devices; and a memory controller that communicates with the plurality of the memory devices through the control bus and the plurality of the data buses, a control latency of the memory device including unrepaired defective memory cells is set differently from a control latency of the other memory devices, where the control latency is used for recognizing control signals of the control bus.

A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.