The invention provides a system capable of remotely controlling electronic apparatus, which includes a cloud management platform and at least one electronic apparatus. The electronic apparatus includes at least one operation element, and a data storage device having a network communication function. The data storage device includes a first transmission interface, a second transmission interface, a data storage unit, and an operation management unit. Via the first transmission interface, data stored in the data storage unit can be read or data can be written into the data storage unit. The operation management unit of the data storage device transmits a specific operation instruction to the operation element via the second transmission interface after receiving the specific operation instruction sent from the cloud management platform, such that the operation element can execute a corresponding operation according to the specific operation instruction.

An interface device between a plurality of memory devices and a memory controller includes processing circuitry configured to provide a plurality of controller channels for communicating with the memory controller, to provide a plurality of memory channels for communicating with the plurality of memory devices, and to connect each of the plurality of controller channels to at least one of the plurality of memory channels in a first mode and disconnect the plurality of controller channels from the plurality of memory channels in a second mode.

An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

An interface circuit of a memory device including a plurality of memory dies including a plurality of registers corresponding to the plurality of memory dies, respectively, the plurality of registers each configured to store command information related to a data operation command, a demultiplexer circuit configured to provide input command information to a selected register from among the plurality of registers according to at least one of a first address or a first chip selection signal, the input command information being received from outside the interface circuit, and a multiplexer circuit configured to receive output command information from the selected register from among the plurality of registers and output the output command information according to at least one of a second address or a second chip selection signal may be provided.

The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

Disclosed herein is a solid-state storage device that reduces read time for read time-sensitive data (“RTS data”). Data-characterizing logic characterizes incoming data from a host system as primary data including the RTS data or secondary data including non-RTS data. Memory-cell programming schemes include a primary data-programming scheme for a reduced read-frequency zone for the primary data and a secondary data-programming scheme standard read-frequency zone for the secondary data. Data routing logic routes the primary data to a plurality of physical pages corresponding to lower logical pages of a plurality of logical pages in the at-least-one reduced read-frequency zone with assistance by a logical-to-physical address translator. The lower logical pages require fewer read operations than upper logical pages of the plurality of logical pages to read the primary data, which results in a reduction of the read time for the RTS data in the at-least-one reduced read-frequency zone.

Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

Methods, systems, and devices for dynamic channel mapping for a memory system are described. In one example, a memory system may include a memory device having a first set of pins that are associated with a channel, and a host device, coupled with the memory device, having a second set of pins that are associated with the channel. The host device may include a controller configured to receive signaling from the memory device for a channel mapping operation, determine a channel mapping (e.g., a mapping of pins, a mapping between pins of the channel and information positions of the channel) based at least in part on the received signaling, and communicate information with the memory device via the channel based at least in part on the determined channel mapping.

A data forwarding chip and a server are disclosed. The server includes a data forwarding chip, a network interface card, and a processor. The data forwarding chip is separately connected to the network interface card and the processor through a bus. After receiving a data forwarding request sent by the processor or the network interface card, the data forwarding chip forwards, based on a destination address of the data forwarding request through an endpoint port that is on the forwarding chip and that is directly connected to a memory space corresponding to the destination address of the data forwarding request, to-be-forwarded data specified in the data forwarding request, such that when the server sends or receives data, cross-chip transmission of data between processors occurs, thereby reducing a data transmission delay.

A cache system having cache sets, registers associated with the cache sets respectively, and a logic circuit coupled to a processor to control the cache sets according to the registers. When a connection to an address bus of the system receives a memory address from the processor, the logic circuit can be configured to: generate an extended tag from at least the memory address; and determine whether the generated extended tag matches with a first extended tag for a first cache set or a second extended tag for a second cache set of the system. Also, the logic circuit can also be configured to implement a command received from the processor via the first cache set in response to the generated extended tag matching with the first extended tag and via the second cache set in response to the generated extended tag matching with the second extended tag.