An integrated circuit (IC) includes a memory manager having a plurality of memory ports, each configured to communicate with a corresponding floating memory block. The IC includes a first interconnect for a first domain, wherein the first interconnect has a first set of fixed ports configured to communicate with memory blocks dedicated to the first domain and a first set of floating ports configured to communicate with the memory manager, and a second interconnect for a second domain, wherein the second interconnect has a second set of fixed ports configured to communicate with memory blocks dedicated to the second domain and a second set of floating ports configured to communicate with the memory manager. The memory manager is configured to allocate a first portion of the memory ports to the first set of floating ports and a second portion of the memory ports to the second set of floating ports.

Various embodiments provide a memory system architecture for heterogeneous memory technologies, which can be implemented by a memory sub-system. A memory system architecture of some embodiments can support servicing an individual command request using different (heterogeneous) memory technologies, such as different types of memory devices (e.g., heterogeneous memory devices), different types of memory device controllers (e.g., heterogeneous memory device controllers), different types of data paths (e.g., data paths with different protocols or protocol constrains), or some combination thereof. According to various embodiments, the memory system architecture uses tracking and management of multiple command responses to service a single command request from a host system.

A differential Data Strobe (DQS) signal is used to transmit and receive Cyclic Redundancy Check (CRC) between a host memory controller and a memory module. The differential DQS strobe signal is trained before it is used for transactions. The training is performed by sending and receiving a CRC pattern on the differential DQS strobe signal between the host memory controller and a buffer in the memory module.

According to embodiments of the present disclosure, there is provided a data transmission apparatus. The data transmission apparatus includes a plurality of first ports, a plurality of second ports, and a plurality of data channels. The plurality of first ports are coupled to a processing unit. The plurality of second ports are coupled to a plurality of memories. The plurality of data channels are disposed among the first ports and the second ports to form an interleaving network having a plurality of layers, and configured to transmit data among the processing unit and the plurality of memories, such that each layer in the interleaving network includes at least one interleaving sub-network.

A cache system, having a first cache, a second cache, and a logic circuit coupled to control the first cache and the second cache according to an execution type of a processor. When an execution type of a processor is a first type indicating non-speculative execution of instructions and the first cache is configured to service commands from a command bus for accessing a memory system, the logic circuit is configured to copy a portion of content cached in the first cache to the second cache. The cache system can include a configurable data bit. The logic circuit can be coupled to control the caches according to the bit. Alternatively, the caches can include cache sets. The caches can also include registers associated with the cache sets respectively. The logic circuit can be coupled to control the cache sets according to the registers.

Dynamic random access memory (DRAM) data may be accessed by a memory controller using a broadcast mode or a non-broadcast mode. In the broadcast mode, a first portion of data that is the subject of an access request and a second portion of the data that is the subject of the access request may be accessed concurrently via first and second pseudo-channels, respectively. In the non-broadcast mode, data that is the subject of the access request may be accessed via a selected one of the first and second pseudo-channels.

A storage system and method for dynamic selection of a host interface are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive, from a host, a selection of a first host interface; in response to receiving the selection of the first host interface, implement the first host interface; after the first host interface has been implemented, receive, from the host, a selection of a second host interface; and in response to receiving the selection of the second host interface, implement the second host interface even though the first host interface was previously implemented. Other embodiments are provided.

A network storage device connected with a network fabric includes a network storage controller that performs interfacing with the network fabric and translates and processes a command provided through the network fabric, and a nonvolatile memory cluster that exchanges data with the network storage controller under control of the network storage controller. The nonvolatile memory cluster includes a first nonvolatile memory array connected with the network storage controller through a first channel, a nonvolatile memory switch connected with the network storage controller through a second channel, and a second nonvolatile memory array communicating with the network storage controller under control of the nonvolatile memory switch.

Systems, apparatuses, and methods related to memory systems and operation are described. A memory system may be coupled to a processor, which includes a memory controller. The memory controller may determine whether targeting of first data and second data by the processor to perform an operation results in processor-side cache misses. When targeting of the first data and the second data result in processor-side cache misses, the memory controller may determine a single memory access request that requests return of both the first data and the second data and instruct the processor to output the single memory access request to a memory system via one or more data buses coupled between the processor and the memory system to enable processing circuitry implemented in the processor to perform the operation based at least in part on the first data and the second data when returned from the memory system.

Systems, apparatuses, and methods related to memory systems and operation are described. A memory system may be communicative coupled to a processor via one or more data buses. Additionally, the memory system may include one or more memory devices that store data to be used by processing circuitry implemented in the processor to perform an operation. Furthermore, the memory system may include a memory controller that receives a memory access request that return of the data via the one or more data buses and, in response, determines a storage location of the data in the one or more memory devices based at least in part on the memory access request and instructs the memory system to store the data directly into a processor-side cache integrated with the processing circuitry to enable the processing circuitry implemented in the processor to perform the operation based on the data.