This invention provides a system having a processor assembly interconnected to a memory bus and a memory-storage combine, interconnected to the memory bus. The memory-storage combine is adapted to allow access, through the memory bus, a combination of random access memory (RAM) based data storage and non-volatile mass data storage. A controller is arranged to address the both RAM based data storage and the non-volatile mass data storage as part of a unified address space in the manner of RAM.

A multi-rank memory bus architecture is provided in which an active DRAM is unterminated and an inactive DRAM terminates to increase the data eye width at the active DRAM.

A storage device may include a memory; and a controller. The controller may be configured to: maintain, for each respective type of command segment of a plurality of types of command segments, a respective timer of a plurality of timers that indicates an amount of time elapsed since the controller last output a command segment of the respective type of command segments to the memory; determine, based on the plurality of timers, whether a command segment of a particular type of command segment of the plurality of types of command segments may be output to the memory at a current time; and responsive to determining that the command segment of the particular type of command segment may be output at the current time, permit output of the command segment of the particular type of command segment to the memory at the current time.

Systems and methods are disclosed for configuring an interface bridge. A computing system includes a device controller, an interface bridge module coupled to the device controller configured to provide bridge functionality according to a first communication standard, a primary communication interface conforming to the first communication standard and coupled to the interface bridge module. The computing system further includes a first non-volatile memory module coupled to the interface bridge module, the first non-volatile memory module storing first stage boot loader code, a second non-volatile memory module coupled to the device controller, and a secondary communication interface conforming to a second communication standard coupled to the device controller. The device controller is configured to receive update package data over the secondary communication interface, the update package data including a firmware image, and write the update package data to the second non-volatile memory module.

In a method of operating a memory device, a first write command, a first write address, and first write data are received by a first memory device through a channel. The first write command, received by the first memory device, is sensed by a controller. The controller is connected to the channel and controls a second memory device. The first memory device and the second memory device are different types of memory devices. When the first write command is sensed by the controller, a first write log is generated using the first write address and the first write data. The first write log is stored into a buffer.

An instruction can be received at a sequencer from a controller. The sequencer can be in a package including the sequencer and one or more memory components. The sequencer is operatively coupled to a controller that is separate from the package. A processing device of the sequencer can perform an operation based on the instruction on at least one of the one or more memory components in the package.

Techniques for command bus training to a memory device includes triggering a memory device to enter a first or a second command bus training mode, outputting a command/address (CA) pattern via a command bus and compressing a sampled CA pattern returned from the memory device based on whether the memory device was triggered to be in the first or the second command bus training mode.

Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility, or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.

The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

Methods, systems, and devices for addressing scheme for a memory system are described. A memory system may include a plurality of memory devices that are coupled with various command address (CA) channels via respective pins. In some examples, different pins of each memory device may be coupled with different CA channels. When the memory system receives a command to enter a memory device into a per-device addressability (PDA) mode, certain CA channels may be driven. One or more memory devices may enter the PDA mode based on certain pins of the respective memory device being biased.