A method for transmitting data between functions implemented on a first electronic chip of the manycore type. The first electronic chip includes a plurality of execution cores, the execution cores being grouped in clusters, the clusters being interconnected by at least two communication systems. The data transmission method includes the steps of: implementing a first function on a first cluster; implementing a second function on a second cluster, characterised in that the second function is also implemented on a third cluster distinct from the first and second clusters; and transmitting at least one data item between the first function and the second function.

A storage device sharing system and a storage device sharing method are provided. The storage device sharing system includes a storage device, a first chip and a second chip. The first chip and the second chip are configured to enter a toggle mode and an arbitration mode. In the toggle mode, the first chip that acts as the master controls the arbitration potential to a first control potential and a second control potential, and communicates with the storage device in response to the arbitration potential being the first control potential, and the second chip that acts as a slave communicates with the storage device in response to the arbitration potential being the second control potential.

Circuitry comprises a memory to store data defining a set of one or more command queues each associated with a respective memory address space, each command queue defining successive commands for execution from a queue head to a queue tail, the commands being selected from a set of commands comprising synchronization commands and one or more other commands defining memory management operations for a given memory address space, in which completion of a synchronization command is dependent upon one or more completion criteria indicating that all commands from any of the command queues which are earlier than the synchronization command in an execution order have completed; and command processing circuitry to execute the commands; in which the command processing circuitry is configured to maintain a linked list of entries having a list order, each entry defining a respective one of the command queues, in which the command processing circuitry is configured to execute commands at the head of command queues, the command queues being defined by prevailing entries of the linked list of entries in the list order; and in which, for a current occupancy of the linked list at a given stage, the given stage being a given stage of executing commands from command queues defined by entries of the linked list, the command processing circuitry is configured to execute a synchronization command first in the list order and to detect, within that current occupancy of the linked list at the given stage, any further synchronization commands at the head of command queues which are defined by entries of the linked list later in the list order, the command processing circuitry applying, for any such further synchronization commands, the completion criteria of the synchronization command at the head of a given command queue, the given command queue being defined by an entry of the linked list earliest in the list order so as to treat any such further synchronization commands as having been completed.

For polling communication devices in a communication system including a host device and communication devices. The host device is connected to the communication devices via a clock line for transmitting a clock signal to the communication devices and via an arbitration line implemented with OR logic for receiving arbitration signal transmitted by the communication devices. Each communication device is configured to pull up or down the arbitration line for sending an arbitration signal when the communication device is ready to send data to the host device. Each communication device is configured to pull down the arbitration line for sending an arbitration signal when the communication device has no data to send to the host device. The host device (HD) is able to: send a clock signal on the clock line during an arbitration cycle, causing the communication devices to send respective arbitration signals towards the arbitration line, during the arbitration cycle, receive a final signal corresponding to an addition of the arbitration signals, during the arbitration cycle, resulting from the OR logic applied to the arbitration signals, detect the communication devices ready to send data based on the 1 bit of the final signal, select, among the detected communication devices, the communication device associated with the highest priority in a priority table containing the priorities associated with the communication devices, and poll the selected communication device to receive data from the selected communication device during a communication cycle.

Systems and methods for limiting the rate of packet transmission from a NIC to a host CPU are provided. According to one embodiment, data packets are received from a network by the NIC. The NIC is coupled to a host central processing unit (CPU) of a network security device through a bus. A status of the host CPU is monitored by the NIC. A rate limiting mode indicator is set by the NIC based on the status. When the rate limiting mode indicator indicates rate limiting is inactive, then the received data packets are delivered or made available to the host CPU for processing. When the rate limiting mode indicator indicates rate limiting is active, then rate limiting is performing by temporarily stopping or slowing the delivery or making available of the received data packets to the host CPU for processing.

Circuitry comprises a memory to store data defining a set of one or more command queues each associated with a respective memory address space, each command queue defining successive commands for execution from a queue head to a queue tail, the commands being selected from a set of commands comprising synchronization commands and one or more other commands defining memory management operations for a given memory address space, in which completion of a synchronization command is dependent upon one or more completion criteria indicating that all commands from any of the command queues which are earlier than the synchronization command in an execution order have completed; and command processing circuitry to execute the commands; in which the command processing circuitry is configured to maintain a linked list of entries having a list order, each entry defining a respective one of the command queues, in which the command processing circuitry is configured to execute commands at the head of command queues, the command queues being defined by prevailing entries of the linked list of entries in the list order; and in which, for a current occupancy of the linked list at a given stage, the given stage being a given stage of executing commands from command queues defined by entries of the linked list, the command processing circuitry is configured to execute a synchronization command first in the list order and to detect, within that current occupancy of the linked list at the given stage, any further synchronization commands at the head of command queues which are defined by entries of the linked list later in the list order, the command processing circuitry applying, for any such further synchronization commands, the completion criteria of the synchronization command at the head of a given command queue, the given command queue being defined by an entry of the linked list earliest in the list order so as to treat any such further synchronization commands as having been completed.

A bus traffic control apparatus includes a sizing block, a traffic request controller and a bus master engine. The sizing block is configured to determine a data transmitting size of a bus master based on bus traffic information. The traffic request controller is configured to control transmission of data from the bus master based on the data, a destination of the data, the data transmitting size. The bus master engine is configured to transmit the data to the destination in the data transmitting size based on the data, the destination of the data, the data transmitting size and a request received from the traffic request controller.

The present disclosure relates to a distributed console server system. The system may have a server and a software module loaded onto the server for communications with a plurality of remote devices within a data center. A remote serial port unit may be included which is in communication with the server and which is controlled in part by the server and the software module. The remote serial port unit may be in communication with the plurality of remote devices. The remote serial port unit may include at least one of a first module including a plurality of RJ45 ports, or a second module including a plurality of USB ports.

Systems and methods for limiting the rate of packet transmission from a NIC to a host CPU are provided. According to one embodiment, data packets are received from a network by the NIC. The NIC is coupled to a host central processing unit (CPU) of a network security device through a bus. A status of the host CPU is monitored by the NIC. A rate limiting mode indicator is set by the NIC based on the status. When the rate limiting mode indicator indicates rate limiting is inactive, then the received data packets are delivered or make available to the host CPU for processing. When the rate limiting mode indicator indicates rate limiting is active, then rate limiting is performing by temporarily stopping or slowing the delivery or making available of the received data packets to the host CPU for processing.

Systems and methods for limiting the rate of packet transmission from a NIC to a host CPU are provided. According to one embodiment, data packets are received from a network by the NIC. The NIC is coupled to a host central processing unit (CPU) of a network appliance through a bus system. A status of the host CPU is monitored by the NIC. A rate limiting mode indicator is set by the NIC based on the status. When the rate limiting mode indicator indicates rate limiting is inactive, then the received data packets are transmitted from the NIC to the host CPU for processing. When the rate limiting mode indicator indicates rate limiting is active, then rate limiting is performing by temporarily stopping or slowing transmission of the received data packets from the NIC to the host CPU for processing.