The vector data path is divided into smaller vector lanes. A register such as a memory mapped control register stores a vector lane number (VLX) indicating the number of vector lanes to be powered. A decoder converts this VLX into a vector lane control word, each bit controlling the ON of OFF state of the corresponding vector lane. This number of contiguous least significant vector lanes are powered. In the preferred embodiment the stored data VLX indicates that 2.sup.VLX contiguous least significant vector lanes are to be powered. Thus the number of vector lanes powered is limited to an integral power of 2. This manner of coding produces a very compact controlling bit field while obtaining substantially all the power saving advantage of individually controlling the power of all vector lanes.

The vector data path is divided into smaller vector lanes. A register such as a memory mapped control register stores a vector lane number (VLX) indicating the number of vector lanes to be powered. A decoder converts this VLX into a vector lane control word, each bit controlling the ON of OFF state of the corresponding vector lane. This number of contiguous least significant vector lanes are powered. In the preferred embodiment the stored data VLX indicates that 2.sup.VLX contiguous least significant vector lanes are to be powered. Thus the number of vector lanes powered is limited to an integral power of 2. This manner of coding produces a very compact controlling bit field while obtaining substantially all the power saving advantage of individually controlling the power of all vector lanes.

A computing system may implement a low priority arbitration interrupt method that includes receiving a message signaled interrupt (MSI) message from an input output hub (I/O hub) transmitted over an interconnect fabric, selecting a processor to interrupt from a cluster of processors based on arbitration parameters, and communicating an interrupt service routine to the selected processor, wherein the I/O hub and the cluster of processors are located within a common domain.

A multicore processor system includes core configured to detect a process assignment instruction; acquire a remaining time obtained by subtracting a processing time of interrupt processing assigned to an arbitrary core of a multicore processor from a period that is from a calling time of the interrupt processing to an execution time limit of the interrupt processing, upon detecting the process assignment instruction; judge if the remaining time acquired at the acquiring is greater than or equal to a processing time of processing defined to limit an interrupt in the process; and assign the process to the arbitrary core, upon judging that the remaining time is greater than or equal to the processing time of the processing defined to limit an interrupt in the process.

A multicore processor system includes core configured to detect a process assignment instruction; acquire a remaining time obtained by subtracting a processing time of interrupt processing assigned to an arbitrary core of a multicore processor from a period that is from a calling time of the interrupt processing to an execution time limit of the interrupt processing, upon detecting the process assignment instruction; judge if the remaining time acquired at the acquiring is greater than or equal to a processing time of processing defined to limit an interrupt in the process; and assign the process to the arbitrary core, upon judging that the remaining time is greater than or equal to the processing time of the processing defined to limit an interrupt in the process.

The exemplary embodiments described herein relate to systems and methods for operating system aware low latency handling. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of receiving a fast interrupt request asserted by a hardware device while the processor is executing within a kernel critical section, executing a fast interrupt handler at a first priority level, raising a second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service and processing the second priority level interrupt once the processor has executed the kernel critical section.

The exemplary embodiments described herein relate to systems and methods for operating system aware low latency handling. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of receiving a fast interrupt request asserted by a hardware device while the processor is executing within a kernel critical section, executing a fast interrupt handler at a first priority level, raising a second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service and processing the second priority level interrupt once the processor has executed the kernel critical section.

Systems and methods to share a plurality of virtual network interface controllers (vNICs) amongst a plurality of hosts 104 are described. The described methods are implemented in a network sharing system (NISS) (102) including a programmable vNIC cluster (204) comprising the plurality of vNICs, where a set of vNICs from amongst the plurality of vNICs is dynamically configured to communicate with a host (104-1) from amongst the plurality of hosts (104). Further, the NISS (102) includes a multi-host peripheral component interconnect (PCI) express (PCIe) interface and mapper (MHIP) (202) coupled to the programmable vNIC cluster (204), to receive data packets from the set of vNICs, wherein the set of vNICs comprises one or more vNICs; and provide the data packets from the set of vNICs to the host (104-1) based on demultiplexing of the data packets.

Systems and methods to share a plurality of virtual network interface controllers (vNICs) amongst a plurality of hosts 104 are described. The described methods are implemented in a network sharing system (NISS) (102) including a programmable vNIC cluster (204) comprising the plurality of vNICs, where a set of vNICs from amongst the plurality of vNICs is dynamically configured to communicate with a host (104-1) from amongst the plurality of hosts (104). Further, the NISS (102) includes a multi-host peripheral component interconnect (PCI) express (PCIe) interface and mapper (MHIP) (202) coupled to the programmable vNIC cluster (204), to receive data packets from the set of vNICs, wherein the set of vNICs comprises one or more vNICs; and provide the data packets from the set of vNICs to the host (104-1) based on demultiplexing of the data packets.

A method for selecting a substantially optimized scheduler from a plurality of schedulers for executing dispersed storage error functions on a distributed storage network begins with a computing device receiving a dispersed storage error functions along with an indication of measured throughput and measured latency from a requesting device. The method resumes when a scheduler is selected from the plurality of schedulers based on desired latency and throughput, while considering the characteristics of the dispersed error function being executed. The method continues with the computing device receiving a different dispersed error function and selecting a different scheduler.