A system and method of implementing a modified priority routing of an input/output (I/O) interruption. The system and method determines whether the I/O interruption is pending for a core and whether any of a plurality of guest threads of the core is enabled for guest thread processing of the interruption in accordance with the determining that the I/O interruption is pending. Further, the system and method determines whether at least one of the plurality of guest threads enabled for guest thread processing is in a wait state and, in accordance with the determining that the at least one of the plurality of guest threads enabled for guest thread processing is in the wait state, routes the I/O interruption to a guest thread enabled for guest thread processing and in the wait state.

A system and method of implementing a modified priority routing of an input/output (I/O) interruption. The system and method determines whether the I/O interruption is pending for a core and whether any of a plurality of guest threads of the core is enabled for guest thread processing of the interruption in accordance with the determining that the I/O interruption is pending. Further, the system and method determines whether at least one of the plurality of guest threads enabled for guest thread processing is in a wait state and, in accordance with the determining that the at least one of the plurality of guest threads enabled for guest thread processing is in the wait state, routes the I/O interruption to a guest thread enabled for guest thread processing and in the wait state.

The present invention is a novel RTOS/OS architecture that changes the fundamental way that context switching is performed. In all prior operating system implementations, context switching required disabling of interrupts. This opens the possibility that data can be lost. This novel approach consists of a context switching method in which interrupts are never disabled. Two implementations are presented. In the first implementation, the cost is a negligible amount of memory. In the second, the cost is only a minimal impact on the context switching time. This RTOS/OS architecture requires specialized hardware. Concretely, an advanced interrupt controller that supports nesting and tail chaining of prioritized interrupts is needed (e.g. the Nested Vectored Interrupt Controller (NVIC) found on many ARM processors). The novel RTOS/OS architecture redefines how task synchronization primitives such as semaphores and mutexes are released. Whereas previous architectures directly accessed internal structures, this architecture does so indirectly by saving information in shared buffers or setting flags, and then activating a low priority software interrupt that subsequently interprets this data and performs all context switching logic. The software interrupt must be set as the single lowest priority interrupt in the system.

The present invention is a novel RTOS/OS architecture that changes the fundamental way that context switching is performed. In all prior operating system implementations, context switching required disabling of interrupts. This opens the possibility that data can be lost. This novel approach consists of a context switching method in which interrupts are never disabled. Two implementations are presented. In the first implementation, the cost is a negligible amount of memory. In the second, the cost is only a minimal impact on the context switching time. This RTOS/OS architecture requires specialized hardware. Concretely, an advanced interrupt controller that supports nesting and tail chaining of prioritized interrupts is needed (e.g. the Nested Vectored Interrupt Controller (NVIC) found on many ARM processors). The novel RTOS/OS architecture redefines how task synchronization primitives such as semaphores and mutexes are released. Whereas previous architectures directly accessed internal structures, this architecture does so indirectly by saving information in shared buffers or setting flags, and then activating a low priority software interrupt that subsequently interprets this data and performs all context switching logic. The software interrupt must be set as the single lowest priority interrupt in the system.

In one or more embodiments, one or more systems, methods, and/or processes may configure multiple link registers, of a first semiconductor package of an information handling system (IHS), that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of multiple components of the first semiconductor package to multiple inter-processor communication link interfaces; may communicate with a second semiconductor package of the IHS via the multiple inter-processor communication link interfaces; may determine that a link utilization value of multiple link utilization values is at or above a threshold value; and may configure a link register of the multiple link registers, associated with the at least one component of the multiple components, that configures the I/O communication fabric to route communications of the at least one component of the multiple components to a second inter-processor communication link interface of the multiple inter-processor communication link interfaces.

In one or more embodiments, one or more systems, methods, and/or processes may configure multiple link registers, of a first semiconductor package of an information handling system (IHS), that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of multiple components of the first semiconductor package to multiple inter-processor communication link interfaces; may communicate with a second semiconductor package of the IHS via the multiple inter-processor communication link interfaces; may determine that a link utilization value of multiple link utilization values is at or above a threshold value; and may configure a link register of the multiple link registers, associated with the at least one component of the multiple components, that configures the I/O communication fabric to route communications of the at least one component of the multiple components to a second inter-processor communication link interface of the multiple inter-processor communication link interfaces.

According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device. The memory controller is configured to, when the first request is received from the host device while causing the nonvolatile memory to execute a second process, hold interruption of the second process until a first number becomes a first threshold value or more. The first number is a number of the first requests to be performed in the memory controller. The first threshold value is an integer of 2 or more.

The vector data path is divided into smaller vector lanes. A register such as a memory mapped control register stores a vector lane number (VLX) indicating the number of vector lanes to be powered. A decoder converts this VLX into a vector lane control word, each bit controlling the ON of OFF state of the corresponding vector lane. This number of contiguous least significant vector lanes are powered. In the preferred embodiment the stored data VLX indicates that 2.sup.VLX contiguous least significant vector lanes are to be powered. Thus the number of vector lanes powered is limited to an integral power of 2. This manner of coding produces a very compact controlling bit field while obtaining substantially all the power saving advantage of individually controlling the power of all vector lanes.

The vector data path is divided into smaller vector lanes. A register such as a memory mapped control register stores a vector lane number (VLX) indicating the number of vector lanes to be powered. A decoder converts this VLX into a vector lane control word, each bit controlling the ON of OFF state of the corresponding vector lane. This number of contiguous least significant vector lanes are powered. In the preferred embodiment the stored data VLX indicates that 2.sup.VLX contiguous least significant vector lanes are to be powered. Thus the number of vector lanes powered is limited to an integral power of 2. This manner of coding produces a very compact controlling bit field while obtaining substantially all the power saving advantage of individually controlling the power of all vector lanes.

In various implementations, provided are systems and methods for an integrated circuit including a completer device, a requester device, and an interconnect fabric. The requester device is configured to generate transactions to the completer device, where each transaction includes a request packet that includes an attribute associated with the completer device; and the interconnect fabric is coupled to the requester device and the completer device. The integrated circuit can also include a QoS regulator configured to identify, based on a first attribute associated with the completer device, a first QoS value establishing a first priority level for a first request packet generated by the requester device, and modify the first request packet to include the first QoS value.