Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

An interrupt system for RISC-V architecture includes an original register in a CLIC, a pushmcause register, a pushmepc register, an interrupt response register, and an mtvt2 register; the pushmcause register is used to store a value in an mcause on a stack by means of an instruction; the pushmepc register is used to store a value in an mepc on a stack by means of an instruction; the interrupt response register is used to respond to a non-vectored interrupt request issued by a CLIC by means of an instruction, obtain an interrupt subroutine entry address, and modify a global interrupt enable; and the mtvt2 register is used to store a base address of an non-vectored interrupt in a CLIC mode.

The invention provides a USB device and a data transfer method thereof. The USB device is coupled to a host and transfers at least one packet to the host. The USB device includes a memory, a USB controller, and a transfer management circuit. The memory stores packets. The USB controller is configured to transfer the packets to the host. The transfer management circuit is coupled between the memory and the USB controller and configured to sequentially read the packets from the memory and sequentially transfer the packets to the USB controller, and to perform the following operations: ending the data transfer when a stored content of the memory does not meet a condition for continuing packet transfer; or ending the data transfer when a last transferred packet meets a preset condition and a next packet that follows the last transferred packet does not meet the preset condition.

The invention provides a USB device and a data transfer method thereof. The USB device is coupled to a host and transfers at least one packet to the host. The USB device includes a memory, a USB controller, and a transfer management circuit. The memory stores packets. The USB controller is configured to transfer the packets to the host. The transfer management circuit is coupled between the memory and the USB controller and configured to sequentially read the packets from the memory and sequentially transfer the packets to the USB controller, and to perform the following operations: ending the data transfer when a stored content of the memory does not meet a condition for continuing packet transfer; or ending the data transfer when a last transferred packet meets a preset condition and a next packet that follows the last transferred packet does not meet the preset condition.

Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.