A system includes a multiplexer, an input/output (I/O) pin, a logic circuit, and a control register. The multiplexer has multiple inputs, an output, and a selection input. The logic circuit is coupled between the multiplexer and the I/O pin. The logic circuit has a first input. The control register includes first and second bit fields corresponding to the I/O pin. The first bit field is coupled to the selection input of the multiplexer, and the second bit field is coupled to the first input of the logic circuit.

The systems and methods are configured to efficiently and effectively access memory. In one embodiment, a memory controller comprises a request queue, a buffer, a control component, and a data path system. The request queue receives memory access requests. The control component is configured to process information associated with access requests via a first narrow memory channel and a second narrow memory channel. The first narrow memory channel and the second narrow memory channel can have a portion of command/control communication lines and address communication lines that are included in and shared between the first narrow memory channel and the second narrow memory channel. The data path system can include a first data module and one set of unshared data lines associated with the first memory channel and a second data module and another set of unshared data lines associated with second memory channel.

An information handling system may include a bus initiator, a plurality of bus endpoints, and a single-wire bus communicatively coupled between the bus initiator and the plurality of bus endpoints, wherein the bus comprises a multiplexer. The bus initiator may be configured to perform in-band addressing to select a communications channel through the multiplexer via an addressing protocol that uses pulse bursts for initiation of the addressing, identification of the communications channel, and termination of the addressing. Pulses of the pulse bursts may be sufficiently short in duration to pass through filters of the bus endpoints such that the pulse bursts are not processed by the bus endpoints.

A functional node for an information transmission network and corresponding network are disclosed. In one aspect, the functional node includes at least one module for distributing messages between input and output ports. The distribution module includes at least one combination of at least three ports, including a first input port connected to a second output port by a first capability for unconditionally propagating messages, not depending on the messages. The first and/or second ports are connected to a third port by a second capability for conditionally propagating messages, depending on the messages.

An embodiment may involve non-volatile memory configured to store chunks of data packets, wherein the chunks are associated with sequence numbers; a shared producer queue; one or more processors configured to transfer the chunks to the shared producer queue in order of the sequence numbers; an array of n sets of processors configured to: (i) read the chunks from the shared producer queue, (ii) re-write network addresses within the data packets to create modified chunks, and (iii) write the modified chunks to queues; and a field programmable gate array based network interface containing the queues and m physical ports, and configured to: (i) read the modified chunks in order of their sequence numbers, (ii) unpack the modified chunks into data packets, (iii) write updated checksums to the data packets, (iv) respectively select output ports for the data packets, and (v) transmit the data packets from the selected output ports.

The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

A system, USB Type-C connector and method are provided herein to transmit encoded data across a USB cable from a transmitter circuit included within a transmitting port of a USB Type-C connector. The method described herein may generally include detecting a voltage generated at a configuration channel (CC) pin of a transmitting port of a USB Type-C connector, setting a voltage at an output node of the transmitter circuit equal to the voltage detected at the CC pin before the output node of the transmitter circuit is connected to the CC pin, subsequently connecting the output node of the transmitter circuit to the CC pin, and transmitting the encoded data from the transmitter circuit through the CC pin to the USB cable.

An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.

Methods and apparatus for data aggregation and multiplexing of one or more virtual bus interfaces via a physical bus interface. Various disclosed embodiments are configured to: (i) multiplex multiple logical interfaces over a single physical interface, (ii) exchange session management and logical interface control, (iii) manage flow control, (iv) provide “hints” about the data (e.g., metadata), and/or (v) pad data packets. In one particular implementation, the methods and apparatus are configured for use within a wireless-enabled portable electronic device, such as for example a cellular-enabled smartphone, and make use of one or more features of a high-speed serialized physical bus interface.

The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.