In accordance with an embodiment, a method of operating a bus interface circuit includes detecting a start sequence on a plurality of input terminals, determining whether a first input terminal and a second input terminal is a data terminal and a clock terminal, respectively, or whether the first input terminal and the second terminal is a clock terminal and a data terminal, respectively. The method also includes routing the first input terminal to a data terminal and the second input terminal to a clock terminal if first input terminal and the second input terminal are determined to be a data terminal and a clock terminal, respectively, and routing the first input terminal to the clock terminal and the second input terminal to the data terminal if first input terminal and the second input terminal are determined to be a clock terminal and a data terminal, respectively.

An embodiment may involve receiving a chunk and a chunk index, where the chunk contains packets captured by a network interface unit and the chunk index contains timestamps of first and last packets within the chunk. The chunk may be stored in a first ring buffer of a first memory and the chunk index may be stored in an index buffer of the first memory. A processor may allocate an entry in an I/O queue of a second memory and an entry in a chunk processing queue of the first memory. The processor may read the chunk processing queue to identify and copy the chunk from the first ring buffer to a location in a second ring buffer of the second memory, the location associated with the entry in the I/O queue. The same or a different processor may instruct a controller to write the chunk to a non-volatile memory unit.

A communication control device according to an embodiment includes one or more hardware processors functioning as a transmission control unit and a communication unit. The transmission control unit performs control of transmission of messages by opening and closing a gate based on transmission permission information. The transmission permission information is generated based on gate control information including a plurality of entries for determining whether to open a plurality of gates corresponding to a plurality of queues. The transmission permission information indicates an amount of transmittable messages in a period corresponding to one or more continuous entries. The communication unit transmits and receives messages in accordance with the control of the transmission control unit.

A system includes a multiplexer, an input/output (I/O) pin, a logic circuit, and a control register. The multiplexer has multiple inputs, an output, and a selection input. The logic circuit is coupled between the multiplexer and the I/O pin. The logic circuit hays a first input. The control register includes first and second bit fields corresponding to the I/O pin. The first bit field is coupled to the selection input of the multiplexer, and the second bit field is coupled to the first input of the logic circuit.

An information handling system may include a bus initiator, a plurality of bus endpoints, and a single-wire bus communicatively coupled between the bus initiator and the plurality of bus endpoints, wherein the bus comprises a multiplexer. The bus initiator may be configured to perform in-band addressing to select a communications channel through the multiplexer via an addressing protocol that uses pulse bursts for initiation of the addressing, identification of the communications channel, and termination of the addressing. Pulses of the pulse bursts may be sufficiently short in duration to pass through filters of the bus endpoints such that the pulse bursts are not processed by the bus endpoints.

The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

A data processing device includes: 1) Fast Fourier Transform (FFT) logic configured to generate FFT output samples for each of a plurality of digital input signals; 3) a first memory device with a plurality of banks; 4) a second memory device; 5) a bit-reversed address generator and first set of circular shift components configured to shift between the plurality of banks when writing the generated FFT output samples in bit-reversed address order to the first memory device; and 6) a second set of circular shift components configured to shift between the plurality of banks when reading FFT output samples in linear address order from the first memory device for storage in the second memory device, wherein the first and second set of circular shift components together are configured to read FFT output samples in transpose order using combined bit-reversal and memory transpose operations.

A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.

Disclosed in some examples are methods, systems, memory controllers, devices, and machine-readable mediums which minimize this stall time by returning a memory write acknowledgement once a write command has been selected by the memory controller input multiplexor rather than when the memory write command has been performed. Because the memory controller enforces an ordering to memory once the packet has been selected at an input multiplexor, ordering of prior and subsequent requests to the same address location are preserved and providing the response early allows the processor to continue its operations earlier without any harmful effects.

A data processing device includes: 1) Fast Fourier Transform (FFT) logic configured to generate FFT output samples for each of a plurality of digital input signals; 3) a first memory device with a plurality of banks; 4) a second memory device; 5) a bit-reversed address generator and first set of circular shift components configured to shift between the plurality of banks when writing the generated FFT output samples in bit-reversed address order to the first memory device; and 6) a second set of circular shift components configured to shift between the plurality of banks when reading FFT output samples in linear address order from the first memory device for storage in the second memory device, wherein the first and second set of circular shift components together are configured to read FFT output samples in transpose order using combined bit-reversal and memory transpose operations.