An interrupt controlled prefetching and caching technique includes transferring peripheral data from a peripheral to a peripheral cache via direct memory access in response to receiving an interrupt request from the peripheral. The technique includes executing an interrupt service routine prologue in response to completion of transferring of peripheral data. The technique may include providing a base address and a transfer trigger to initiate the transferring of the peripheral data. The technique may include executing a peripheral interrupt service routine after executing the interrupt service routine prologue. The technique may include executing an interrupt service routine epilogue after executing the peripheral interrupt service routine, the interrupt service routine epilogue including resetting an interrupt status flag associated with the interrupt request. Executing the interrupt service routine may include executing instructions using the peripheral data at a rate at least an order of magnitude faster than an access time of the peripheral.

An interrupt controlled prefetching and caching technique includes transferring peripheral data from a peripheral to a peripheral cache via direct memory access in response to receiving an interrupt request from the peripheral. The technique includes executing an interrupt service routine prologue in response to completion of transferring of peripheral data. The technique may include providing a base address and a transfer trigger to initiate the transferring of the peripheral data. The technique may include executing a peripheral interrupt service routine after executing the interrupt service routine prologue. The technique may include executing an interrupt service routine epilogue after executing the peripheral interrupt service routine, the interrupt service routine epilogue including resetting an interrupt status flag associated with the interrupt request. Executing the interrupt service routine may include executing instructions using the peripheral data at a rate at least an order of magnitude faster than an access time of the peripheral.

A programmable system arbiter for granting access to a system bus among a plurality of arbiter clients and a central processing unit is disclosed. The programmable system arbiter may include one or more interrupt priority registers, each of the one or more interrupt priority registers associated with an interrupt type; and system arbitration logic operable to arbitrate access to the system bus among the plurality of arbiter clients and the CPU based at least on an analysis of a programmed priority order, the programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of a plurality of operating modes of the central processing unit, and each of the one or more interrupt types.

A distributed control system includes a tree topology network or a daisy-chain network including a communication parent station, communication child stations, and a plurality of communication paths among the communication parent station and the communication child stations, in which the communication parent station and the communication child stations include a scheduling unit that controls a transfer cycle that is temporal intervals of data transfer. The scheduling unit sets the transfer cycle that is the fastest out of a plurality of the data as a reference cycle, counts the number of times each time the reference cycle elapses, and imparts a value of the number of times to the reference cycle as a cycle number. When the cycle number reaches an optional number, the number of times is returned to an initial value, which makes one cycle of transfer control, and the transfer control is repeatedly executed. For the timing of the reference cycle at which the data is transferred, the scheduling unit defines a cycle number to which the reference cycle corresponds, on the basis of first information corresponding to the data.

A distributed control system includes a tree topology network or a daisy-chain network including a communication parent station, communication child stations, and a plurality of communication paths among the communication parent station and the communication child stations, in which the communication parent station and the communication child stations include a scheduling unit that controls a transfer cycle that is temporal intervals of data transfer. The scheduling unit sets the transfer cycle that is the fastest out of a plurality of the data as a reference cycle, counts the number of times each time the reference cycle elapses, and imparts a value of the number of times to the reference cycle as a cycle number. When the cycle number reaches an optional number, the number of times is returned to an initial value, which makes one cycle of transfer control, and the transfer control is repeatedly executed. For the timing of the reference cycle at which the data is transferred, the scheduling unit defines a cycle number to which the reference cycle corresponds, on the basis of first information corresponding to the data.

Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.

Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.

A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.

A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.

A burst buffer appliance is adapted for coupling between a computer system and a file system. The burst buffer appliance comprises a flash memory or other high-speed memory having a substantially lower access time than the file system, and is configured to include a plurality of virtual machines for processing respective different types of input-output operations that involve utilization of the high-speed memory, with each of the virtual machines providing a different performance level for its associated type of input-output operations. The performance levels provided by the plurality of virtual machines may comprise respective different quality of service (QoS) levels for the respective different types of input-output operations, specified in terms of parameters such as latency and throughput rate. A highest QoS level may be provided by a particular virtual machine for operations involving writing checkpoints from the computer system to the high-speed memory.