An apparatus and method are provided for combining trace data from a plurality of trace sources. The apparatus has an input interface to receive trace data from the plurality of trace sources, and an output interface from which to issue a trace stream incorporating the trace data from each of those trace sources. A network of interconnected funnel elements is used to combine the trace data received at the input interface from the plurality of trace sources in order to produce the trace stream. Each funnel element has a plurality of input ports and an output port, and has associated control circuitry to control connection of the input ports to the output port. Each input port is arranged to receive either trace data from one of the trace sources, or trace data output from an output port of another funnel element in the network. The control circuitry is arranged to determine, from information provided by at least one setup transaction received by the control circuitry, control data indicative of a number of trace sources whose trace data is to be routed through each of the input ports of the associated funnel element. The control circuitry then controls the timing allocation of the associated funnel element's output port to each input port in dependence on the control data. This provides a mechanism for hiding the topology of the funnel elements from the various trace sources, so that the proportion of the bandwidth within the trace stream available to each trace source is not dependent on the topology of the funnel elements.

A packet and inspection system for monitoring the performance of one or more flows on a packet network comprises a processor and memory coupled to each other and to a network bus. The memory stores instructions to be executed by the processor and data to be modified by the execution of the instructions. A processor-controlled arbiter is coupled with the processor and the network bus, and upon reception of a packet on the bus or prior to transmission of a packet on the bus for one of said flows, the arbiter requests execution by the processor of selected instructions stored in the memory by providing the processor with the address of the selected instructions in the memory. The memory provides the processor with data associated with the selected instructions, and the processor modifies the data upon execution of the selected instructions.

Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is implemented with each send block associated with a respective FIFO slot. In response to receiving packet data written to the send blocks and detecting the data in those send blocks has egressed from a send context, corresponding freed FIFO slots are detected, and a lowest slot for which credit return indicia has not be returned is determined. The highest slot in a sequence of freed slots from the lowest slot is then determined, and corresponding credit return indicia is returned. In one embodiment an absolute credit return count is implemented for each send context, with an associated absolute credit sent count tracked via software that writes to the PIO send memory, with the two absolute credit counts used for flow control.

An electronic device includes a transmit buffer, a receive buffer, a communication port, and a controller. The controller is to: communicate with a target device via a data link established via the communication port; determine a throughput ratio between the transmit buffer and the receive buffer; in response to a determination that the throughput ratio is above a threshold, transmit a request to the target device to change an aspect of the data link, where the request includes a payload size indicating an amount of data to be transmitted from the electronic device to the target device; and in response to receiving a grant message associated with the request, increase an amount of transmit lanes within the data link from the electronic device to the target device.

Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity. In response to determining that the other integrated circuit is authorized to execute the activity, the processor circuit sends, to the other integrated circuit over a configurable direct connection, an authorization signal authorizing the other integrated circuit to execute the activity.

A method for data transmission control of inter field programmable gate array (FPGA) and an associated apparatus are provided. The method includes: utilizing a first register device to latch a set of data from a first FPGA according to a first clock, wherein the set of data is arranged and divided into multiple sets of partial data according to attributes of payloads and pointers; utilizing a time-division multiplexing (TDM) interface to transmit the multiple sets of partial data from the first register device to a second register device according to a TDM clock at multiple time points, respectively; and utilizing the second register device to sequentially receive the multiple sets of partial data, in order to output the set of data to a second FPGA, wherein the second FPGA operates according to a second clock different from the first clock.

A First Come First Server (FCFS) arbiter that receives a request to utilize a shared resource from a plurality of devices and in response generates a grant value indicating if the request is granted. The FCFS arbiter includes a circuit and a storage device. The circuit receives a first request and a grant enable during a first clock cycle and outputs a grant value. The grant enable is received from a shared resource. The grant value communicated to the source of the first request. The storage device includes a plurality of request buckets. The first request is stored in a first request bucket when the first request is not granted during the first clock cycle and is moved from the first request bucket to a second request bucket when the first request is not granted during a second clock cycle. A granted request is cleared from all request buckets.

In a method for the emergency shutdown of a bus system, and a bus system, having a master module and bus subscribers disposed in series, the master module and the bus subscribers sending data packets to one another with the aid of a data line, the method has the temporally consecutive method steps: in a first method step, a bus subscriber and/or the master module detect(s) an error status, in a second method step, the bus subscriber and/or the master module send(s) an emergency signal to all bus subscribers and to the master module, in a third method step, a further bus subscriber receives the emergency signal, immediately forwards it to an adjacent bus subscriber and simultaneously evaluates it, and in a fourth method step, the further bus subscriber shuts itself down automatically.

Reducing power consumption of communication interfaces by clock frequency scaling and adaptive interleaving of polling is disclosed. In a first aspect, a control system controls transmission of a command via a serial interface at a higher clock frequency. After transmission, the control system and the interface are operated at a lower clock frequency to save power during command execution. In this aspect, a reduction in polling corresponds to the reduction in clock signal frequency. When the command is complete, the interface is operated at the higher frequency to send another command. In a second aspect, after the control system sends a command to the receiving device, polling is suspended and an execution time of the command is tracked. Polling begins when the tracked execution time almost equals an expected completion time. Both aspects disclosed above may be implemented to reduce power consumption in exchange for a small increase in latency.

A system may include a first device and a second device communicatively coupled to the first device via a communications bus, wherein the communications bus comprises a single clock line for transmission of a clock signal from the first device to the second device, a single frame line for transmission of a frame alignment signal from the first device to the second device, and at least one communications channel for serialized communication of payloads of data between the first device and the second device, wherein the payloads of data have at least two different latencies.