Systems and methods for fast activation of slaves during wake up in an audio system allow a master device in an audio system such as a SOUNDWIRE audio system to send system and/or topology information to capable slave devices during a wake up window so that the slaves may start in an active mode rather than a safe mode. In the most recent proposed versions of SOUNDWIRE, there is a check PHY_Num phase. The systems for fast activation of slaves cause a negative differential line to be driven with an encoded signal by the master during a check PHY_Num phase where the encoded signal indicates a fast mode speed. Capable slaves may then begin in a fast mode rather than a safe (and slow) mode. Latency may be reduced by starting in a fast mode, which may improve the user's audio experience.

A packet and inspection system for monitoring the performance of one or more flows on a packet network comprises a processor and memory coupled to each other and to a network bus. The memory stores instructions to be executed by the processor and data to be modified by the execution of the instructions. A processor-controlled arbiter is coupled with the processor and the network bus, and upon reception of a packet on the bus or prior to transmission of a packet on the bus for one of said flows, the arbiter requests execution by the processor of selected instructions stored in the memory by providing the processor with the address of the selected instructions in the memory. The memory provides the processor with data associated with the selected instructions, and the processor modifies the data upon execution of the selected instructions.

System and method for sharing a PCIe endpoint device with a plurality of host computers, by allocating a quantum of time to a host computer of a plurality of host computers coupled to a PCIe switch, wherein the quantum of time identifies a duration of time during which the host computer has exclusive access to a shareable PCIe endpoint device coupled to the PCIe switch. Requests from the host computer are transmitted to an emulated PCIe endpoint device of the PCIe switch during the quantum of time and the requests are then redirected from the emulated PCIe endpoint device to the shareable PCIe endpoint device during the quantum of time allocated to the host computer.

In a method for the emergency shutdown of a bus system, and a bus system, having a master module and bus subscribers disposed in series, the master module and the bus subscribers sending data packets to one another with the aid of a data line, the method has the temporally consecutive method steps: in a first method step, a bus subscriber and/or the master module detect(s) an error status, in a second method step, the bus subscriber and/or the master module send(s) an emergency signal to all bus subscribers and to the master module, in a third method step, a further bus subscriber receives the emergency signal, immediately forwards it to an adjacent bus subscriber and simultaneously evaluates it, and in a fourth method step, the further bus subscriber shuts itself down automatically.

A data interface circuit wherein calibration adjustments for data bit capture are made without disturbing normal system operation, is described. A plurality of DLL capture and delay circuits for sampling a trained optimal sampling point as well as leading and trailing sampling points are defined. A first stream of data bits is input to the data interface circuit and using a first calibration method, a first optimal sampling point for sampling the data bits input is established. A second stream of data bits is input to the data interface circuit during normal system operation. A second calibration method is performed that is different from the first, the second calibration method being performed whereby: at least one reference data path is established for sampling transition edges of the second stream of data bits input to the data interface during normal system operation.

A function processing service may receive a request to execute source code. The source code may include instructions to perform a function. The function processing service may determine whether at least one hardware acceleration condition has been satisfied for the function. If at least one hardware acceleration condition has been satisfied, the instructions in the source code may be translated into hardware-specific code corresponding to a hardware circuit. The hardware circuit may be configured based on the hardware-specific code, and the hardware circuit may perform the function. The function processing service may then provide the result obtained from the hardware circuit to the requesting entity.

Provided herein are systems and methods for performing dynamic adaption and correction for internal delays in devices connected to a common time-multiplexed bus. The methods allow devices to operate reliably at a higher bus frequency by correcting for inherent and unknown delays within the components and in the system by measuring the actual delays using multiple readings with the bus. Intrinsic noise and jitter are used to increase the precision of the measurements, thereby essentially using these uncertainties as self-dithering for increased measurement resolution. During adaption, delays may be adjusted in multiple step sizes to speed adaption time.

A serial transmission system includes a first storage circuit, a second storage circuit, a control circuit, and a serial processing circuit. The first storage circuit is configured to store data-to-be-transmitted of a plurality of users. The second storage circuit is coupled to the first storage circuit. The control circuit is configured to control the second storage circuit to receive the data-to-be-transmitted from the first storage circuit. The serial processing circuit is configured to receive the data-to-be-transmitted from the second storage circuit in series, and output a plurality of multi-user packets.

In a method for the emergency shutdown of a bus system, and a bus system, having a master module and bus subscribers disposed in series, the master module and the bus subscribers sending data packets to one another with the aid of a data line, the method has the temporally consecutive method steps: in a first method step, a bus subscriber and/or the master module detect(s) an error status, in a second method step, the bus subscriber and/or the master module send(s) an emergency signal to all bus subscribers and to the master module, in a third method step, a further bus subscriber receives the emergency signal, immediately forwards it to an adjacent bus subscriber and simultaneously evaluates it, and in a fourth method step, the further bus subscriber shuts itself down automatically.

Methods and apparatus for scheduling time sensitive operations among independent processors. In one embodiment, an application processor (AP) determines transmission timing parameters for a baseband processor (BB). Thereafter, the AP can generate and transact generic time-sensitive real time transport (RTP) data with the BB in time for transmission via a Long Term Evolution (LTE) communication stack.