According to one embodiment, there is provided an evaluation apparatus including a first data bus and a transmission device. The transmission device is electrically connected to the first data bus at an output side thereof and configured to receive data and another signal different from the data. The transmission device is configured to supply the data to the first data bus in a first period during which a valid signal is in an active level, and supply the another signal to the first data bus in a second period during which the valid signal is in a non-active level.

A Multi-Chip-Module (MCM) includes an MCM substrate and at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus having a fixed data rate. The DPIC is configured to send data to the DCIC by alternating between (i) first time periods during which the DPIC sends over the bus both produced data and dummy data that together have the fixed data rate of the bus, and (ii) second time periods during which the DPIC sends over the bus only dummy data at the fixed data rate, wherein a rate of the produced date and durations of the first time periods and the second time periods, are preset.

An apparatus may comprise multiplexing circuitry to select an ingress lane from among a plurality of ingress lanes to couple to an egress lane; and retiming circuitry to retime a signal received on the selected ingress lane and transmit the retimed signal on the egress lane.

Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.

A method of implementing a multi-threaded device driver for a computer system is disclosed. A polling device driver is partitioned into a plurality of driver threads for controlling a device of a computer system. The device has a first device state of an unscouted state and a scouted state, and a second device state of an inactive state and an active state. A driver thread of the plurality of driver threads determines that the first device state of the device state is in the unscouted state, and changes the first state of the device to the scouted state. The driver thread further determines that the second device state of the device is in the inactive state and changes the second device state of the device to the active state. The driver thread executes an operation on the device during a pre-determined time slot configured for the driver thread.

A device for controlling a transfer of information from a plurality of electronic components through a communication bus to a host device, comprising a chain of processing blocks connected to the electronic components, each of the processing blocks associated with one, or a set, of the electronic components, which processing blocks are arranged such that during the transfer of information an authorization signal propagates through the chain of processing blocks and, when the authorization signal encounters a processing block associated with one of the electronic components or one of the sets of electronic components which contains an information value to be transferred, effecting the transfer of the information value through the communication bus to the host device. The processing blocks are arranged to coordinate their processing in accordance with a clock signal generated independent of a propagation status of the authorization signal within the chain of processing blocks.

Methods and apparatus for time sensitive data transfer between logical domains. In one embodiment, an user equipment (UE) device has an application processor (AP) coupled to a baseband processor (BB) that operate independently of one another normally, but may cooperate in limited hybrid use scenarios. For example, the BB receives audio packets via a cellular network that are converted to pulse code modulated (PCM) digital audio to be played by the AP. Unfortunately, since the AP and the BB are independently clocked, they will experience some clock drift. As a result, the audio playback may have undesirable artifacts if the drift is not otherwise compensated for. To these ends, the AP and/or BB determine a relative clock drift and compensate for playback by e.g., adding, padding, or deleting audio samples and/or audio packets. Techniques for handover scenarios are also disclosed.

A Multi-Chip-Module (MCM) includes an MCM substrate and at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus having a fixed data rate. The DPIC is configured to send data to the DCIC by alternating between (i) first time periods during which the DPIC sends over the bus both produced data and dummy data that together have the fixed data rate of the bus, and (ii) second time periods during which the DPIC sends over the bus only dummy data at the fixed data rate, wherein a rate of the produced date and durations of the first time periods and the second time periods, are preset.

Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.

Embodiments of the present disclosure are directed toward identifying an indication of a timeout related to a mobile broadband interface model (MBIM) process. The disclosure may also be directed to transmitting, based on the indication of the timeout, an indication of an abort command, wherein the abort command is to provide direction to abort the MBIM process. Other embodiments may be described and/or claimed.