A semiconductor apparatus may include a burst operation sensing unit and the interface circuit. The burst operation sensing unit may be configured to generate operation mode conversion signals based on current operation state information and a level variation of at least one signal transmission line. The interface circuit may include one or more analog circuits enabled according to the operation mode conversion signals.

A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

Methods and systems of AES-centric bus architectures and AES-centric state transfer modes are provided. The bus architecture may be implemented on system-on-chip (SoC) devices in conjunction with existing intellectual property (IP) cores. The bus architecture can include a control-bus with a single master, such as a microprocessor, and a data-bus with a single slave, such as DMA.

Methods and systems of AES-centric bus architectures and AES-centric state transfer modes are provided. The bus architecture may be implemented on system-on-chip (SoC) devices in conjunction with existing intellectual property (IP) cores. The bus architecture can include a control-bus with a single master, such as a microprocessor, and a data-bus with a single slave, such as DMA.

A device, including a low-ohmic circuit path; a normal operation circuit path coupled in parallel with the low-ohmic circuit path; and a circuit element configured to select between the low-ohmic circuit path and the normal operation circuit path.

A device, including a low-ohmic circuit path; a normal operation circuit path coupled in parallel with the low-ohmic circuit path; and a circuit element configured to select between the low-ohmic circuit path and the normal operation circuit path.

A method and architecture for operating with distributed (or segmented) on-chip digital interfaces such as the Inter-Integrated Circuit protocol and a Serial Peripheral Interface protocol. This method and architecture, illustratively, divides the available address space of the digital interface register arrays of a device into one or more segments referred to as a fundamental digital interface circuit. Such segmentation allows for each fundamental digital interface circuit to be placed in proximity of the digitally controlled circuit(s) (e.g., analog circuit(s)) which share some operational connection and for exchanging communication in accordance with a plurality of inputs to the device.

A method and architecture for operating with distributed (or segmented) on-chip digital interfaces such as the Inter-Integrated Circuit protocol and a Serial Peripheral Interface protocol. This method and architecture, illustratively, divides the available address space of the digital interface register arrays of a device into one or more segments referred to as a fundamental digital interface circuit. Such segmentation allows for each fundamental digital interface circuit to be placed in proximity of the digitally controlled circuit(s) (e.g., analog circuit(s)) which share some operational connection and for exchanging communication in accordance with a plurality of inputs to the device.

A method and a system for processing a data conflict are provided that relate to the field of signal interface technologies of an integrated circuit, where the method includes sending a power management bus (PMBus) command to a slave device by using a PMBus, so as to perform power management; when the PMBus command fails to be sent, determining whether the number of times that the PMBus command fails to be sent is greater than or equal to a preset value, where the preset value is configured in advance during system initialization; starting timing if the number of times that the PMBus command fails to be sent is less than the preset value; and resending the PMBus command when timing duration reaches resending time. The present invention is applicable to a scenario in which multiple master devices (Masters) send the PMBus command by using the PMBus.