Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Methods and apparatus to implement communications via a remote terminal unit are disclosed. An example apparatus includes a first central processing unit module to be in communication with a host of a process control system. The example apparatus also includes a first rack including a backplane and a plurality of slots. The plurality of slots includes a master slot to receive the first central processing unit module. The backplane communicatively couples the first central processing unit module to at least one of a first communication module or a first input/output (I/O) module inserted in a second one of the slots. The backplane includes a first communication bus for communication of I/O data and a second communication bus for communication of at least one of maintenance data, pass-through data, product information data, archival data, diagnostic data, or setup data. The first communication bus is independent of the second communication bus.

Methods and apparatus to implement communications via a remote terminal unit are disclosed. An example apparatus includes a first central processing unit module to be in communication with a host of a process control system. The example apparatus also includes a first rack including a backplane and a plurality of slots. The plurality of slots includes a master slot to receive the first central processing unit module. The backplane communicatively couples the first central processing unit module to at least one of a first communication module or a first input/output (I/O) module inserted in a second one of the slots. The backplane includes a first communication bus for communication of I/O data and a second communication bus for communication of at least one of maintenance data, pass-through data, product information data, archival data, diagnostic data, or setup data. The first communication bus is independent of the second communication bus.

An apparatus includes a circuit that includes a communication circuit to communicate information via a link using two communication modes. In the first communication mode, the communication circuit communicates information using a communication protocol. In the second communication mode, the communication circuit communicates information without triggering communication using the communication protocol.

An apparatus includes a circuit that includes a communication circuit to communicate information via a link using two communication modes. In the first communication mode, the communication circuit communicates information using a communication protocol. In the second communication mode, the communication circuit communicates information without triggering communication using the communication protocol.

A data processing system having a master device and a plurality of slave devices uses interconnect circuitry to couple the master device with the plurality of slave devices to enable transactions to be performed by the slave devices upon request from the master device. The master device issues a multi-transaction request identifying multiple transactions to be performed, the multi-transaction request providing a base transaction identifier, a quantity indication indicating a number of transactions to be performed, and address information. Request distribution circuitry within the interconnect circuitry analyses the address information and the quantity indication in order to determine, for each of the multiple transactions, the slave device that is required to perform that transaction. Transaction requests are then issued from the request distribution circuitry to each determined slave device to identify which transactions need to be performed by each slave device. Each determined slave device provides a response to the master device to identify completion of each transaction performed by that determined slave device. Each determined slave device provides its responses independently of the responses from any other determined slave device, and each response includes a transaction identifier determined from the base transaction identifier and transaction specific information. This enables the master device to identify completion of each transaction identified within the multi-transaction request. In an alternative arrangement, the same multi-transaction request approach can be used by a master device to initiate cache maintenance operations within a plurality of cache storage devices. This approach can give rise to significant improvements in efficiency and power consumption within the data processing system.

A data processing system having a master device and a plurality of slave devices uses interconnect circuitry to couple the master device with the plurality of slave devices to enable transactions to be performed by the slave devices upon request from the master device. The master device issues a multi-transaction request identifying multiple transactions to be performed, the multi-transaction request providing a base transaction identifier, a quantity indication indicating a number of transactions to be performed, and address information. Request distribution circuitry within the interconnect circuitry analyses the address information and the quantity indication in order to determine, for each of the multiple transactions, the slave device that is required to perform that transaction. Transaction requests are then issued from the request distribution circuitry to each determined slave device to identify which transactions need to be performed by each slave device. Each determined slave device provides a response to the master device to identify completion of each transaction performed by that determined slave device. Each determined slave device provides its responses independently of the responses from any other determined slave device, and each response includes a transaction identifier determined from the base transaction identifier and transaction specific information. This enables the master device to identify completion of each transaction identified within the multi-transaction request. In an alternative arrangement, the same multi-transaction request approach can be used by a master device to initiate cache maintenance operations within a plurality of cache storage devices. This approach can give rise to significant improvements in efficiency and power consumption within the data processing system.

An optical module configured to control a peer to peer transaction includes a silicon photonics substrate, memory formed on the silicon photonics substrate and configured to store a private key, application circuitry formed on the silicon photonics substrate and coupled to the memory, the application circuitry configured to receive, via an external interface, an electrical signal carrying instructions for executing a transaction, verify the transaction using the private key stored in the memory, and selectively generate a transaction message including information for completing the transaction, and optical communication circuitry formed on the silicon photonics substrate and responsive to the application circuitry, the optical communication circuitry configured to generate an optical signal based on the transaction message and transmit the optical signal to at least one remote entity.

An optical module configured to control a peer to peer transaction includes a silicon photonics substrate, memory formed on the silicon photonics substrate and configured to store a private key, application circuitry formed on the silicon photonics substrate and coupled to the memory, the application circuitry configured to receive, via an external interface, an electrical signal carrying instructions for executing a transaction, verify the transaction using the private key stored in the memory, and selectively generate a transaction message including information for completing the transaction, and optical communication circuitry formed on the silicon photonics substrate and responsive to the application circuitry, the optical communication circuitry configured to generate an optical signal based on the transaction message and transmit the optical signal to at least one remote entity.