In one aspect of the present description, in an input/output (I/O) device having multiple CPUs and multiple I/O ports, a cycle of I/O port rotations is initiated in which each port rotation of the cycle includes rotating an assignment of at least one I/O port from one CPU to a different CPU of a plurality of the CPUs. In the illustrated embodiment, an I/O port assignment for each CPU of the plurality CPUs is rotated for at least a portion of the cycle. Other features and aspects may be realized, depending upon the particular application.

In one aspect of the present description, in an input/output (I/O) device having multiple CPUs and multiple I/O ports, a cycle of I/O port rotations is initiated in which each port rotation of the cycle includes rotating an assignment of at least one I/O port from one CPU to a different CPU of a plurality of the CPUs. In the illustrated embodiment, an I/O port assignment for each CPU of the plurality CPUs is rotated for at least a portion of the cycle. Other features and aspects may be realized, depending upon the particular application.

A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.

A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.

In some embodiments, the invention involves using a weighted arbiter switch to provide fairness in passing input streams through a plurality of input ports to an output port. The weighted arbiter switches may be combined in a hierarchical architecture to enable routing through many levels of switches. Each input port has an associated flow counter to count input stream traffic through the input port. An arbiter switch uses the flow counts and weights from arbiter switches at a lower level in the hierarchy to generate a fairly distributed routing of input streams through the output port. Other embodiments are described and claimed.

In some embodiments, the invention involves using a weighted arbiter switch to provide fairness in passing input streams through a plurality of input ports to an output port. The weighted arbiter switches may be combined in a hierarchical architecture to enable routing through many levels of switches. Each input port has an associated flow counter to count input stream traffic through the input port. An arbiter switch uses the flow counts and weights from arbiter switches at a lower level in the hierarchy to generate a fairly distributed routing of input streams through the output port. Other embodiments are described and claimed.

Arbitration circuitry is provided for allocating up to M resources to N requesters, where M2. The arbitration circuitry comprises group allocation circuitry to control a group allocation in which the N requesters are allocated to M groups of requesters, with each requester allocated to one of the groups; and M arbiters each corresponding to a respective one of the M groups. Each arbiter selects a winning requester from the corresponding group, which is to be allocated a corresponding resource of the M resources. In response to a given requester being selected as the winning requester by the arbiter for a given group, the group allocation is changed so that in a subsequent arbitration cycle the given requester is in a different group to the given group.

Arbitration circuitry is provided for allocating up to M resources to N requesters, where M2. The arbitration circuitry comprises group allocation circuitry to control a group allocation in which the N requesters are allocated to M groups of requesters, with each requester allocated to one of the groups; and M arbiters each corresponding to a respective one of the M groups. Each arbiter selects a winning requester from the corresponding group, which is to be allocated a corresponding resource of the M resources. In response to a given requester being selected as the winning requester by the arbiter for a given group, the group allocation is changed so that in a subsequent arbitration cycle the given requester is in a different group to the given group.

Systems, methods, and apparatus for improving bus latency are described. A method performed at a device coupled to a serial bus includes using a dynamic identifier in a first transaction conducted over a first serial bus. The dynamic identifier includes unique identifier and variable identifier portions. The device participates in a sequence of bus arbitrations until the slave device gains access to the first serial bus or a second serial bus. The value of the variable identifier portion may be increased after each bus arbitration that does not result in a grant of access to the first serial bus, and cleared after each bus arbitration that results in a grant of access to the first serial bus. A second transaction may be conducted over the first serial bus after gaining access to the first serial bus. The value of the dynamic identifier defines slave device priority for bus arbitrations.

Systems, methods, and apparatus for improving bus latency are described. A method performed at a device coupled to a serial bus includes using a dynamic identifier in a first transaction conducted over a first serial bus. The dynamic identifier includes unique identifier and variable identifier portions. The device participates in a sequence of bus arbitrations until the slave device gains access to the first serial bus or a second serial bus. The value of the variable identifier portion may be increased after each bus arbitration that does not result in a grant of access to the first serial bus, and cleared after each bus arbitration that results in a grant of access to the first serial bus. A second transaction may be conducted over the first serial bus after gaining access to the first serial bus. The value of the dynamic identifier defines slave device priority for bus arbitrations.