Examples include the distribution of master device tasks among bus queues. Some examples include distribution of a plurality of tasks of a master device among a plurality of bus queues, each for a respective one of a plurality of busses of a computing system, selection of an arbitration timeout time for a task at a front of one of the bus queues, and a request for access to one of the busses from a bus arbiter.

According to one general aspect, an apparatus may include a network of node circuits and a central arbiter circuit. The network of node circuits is within an integrated circuit, wherein the network includes a plurality of segments. The central arbiter circuit may be configured to schedule a routing of a message between a pair of node circuits in the network, wherein the routing includes a guaranteed latency between the pair of node circuits.

According to one general aspect, an apparatus may include a network of node circuits and a central arbiter circuit. The network of node circuits is within an integrated circuit, wherein the network includes a plurality of segments. The central arbiter circuit may be configured to schedule a routing of a message between a pair of node circuits in the network, wherein the routing includes a guaranteed latency between the pair of node circuits.

In one aspect of the present description, in an input/output (I/O) device having multiple CPUs and multiple I/O ports, a cycle of I/O port rotations is initiated in which each port rotation of the cycle includes rotating an assignment of at least one I/O port from one CPU to a different CPU of a plurality of the CPUs. In the illustrated embodiment, an I/O port assignment for each CPU of the plurality CPUs is rotated for at least a portion of the cycle. Other features and aspects may be realized, depending upon the particular application.

In one aspect of the present description, in an input/output (I/O) device having multiple CPUs and multiple I/O ports, a cycle of I/O port rotations is initiated in which each port rotation of the cycle includes rotating an assignment of at least one I/O port from one CPU to a different CPU of a plurality of the CPUs. In the illustrated embodiment, an I/O port assignment for each CPU of the plurality CPUs is rotated for at least a portion of the cycle. Other features and aspects may be realized, depending upon the particular application.

A method for determining timing constraints in dataflow models is disclosed. The method includes receiving node information specifying a plurality of dataflow nodes, as well as coupling between various ones of the dataflow nodes. The method further comprising receiving timing information specifying timing constraints for at least some of the dataflow nodes. Based on the node information, the couplings between the nodes, and the timing information, a timeline dependency graph (TDG). The timeline dependency graph illustrates a timeline, mappings between nodes with side effects to firing times of those nodes on the timeline, and dependencies between nodes.

A method for determining timing constraints in dataflow models is disclosed. The method includes receiving node information specifying a plurality of dataflow nodes, as well as coupling between various ones of the dataflow nodes. The method further comprising receiving timing information specifying timing constraints for at least some of the dataflow nodes. Based on the node information, the couplings between the nodes, and the timing information, a timeline dependency graph (TDG). The timeline dependency graph illustrates a timeline, mappings between nodes with side effects to firing times of those nodes on the timeline, and dependencies between nodes.

Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.

Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.

Arbitrating among portions of multiple transactions and transmitting a winning portion over one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by-clock cycle basis. By repeatedly performing the above each clock cycle, winning portions are interleaved and transmitted over the multiplicity of virtual channels over multiple clock cycles respectively.