Systems and methods for detecting types of storage drives connected to a controller, which performs backplane or enclosure management. The controller has multiple pins, which includes N analog pins, such as the PRSNT# pins. Each of the N analog pins is electrically connected to a corresponding detecting circuits. Further, 2*N storage drives may be connected to and controlled by the controller in a way such that each analog pin may be connected to two storage drives via a corresponding detecting circuit for detecting a drive type of each storage drive. Each storage drive may be a SATA/SAS storage drive, or a NVMe storage drive. In operation, the controller receives a voltage from each of the N analog pins, and determines the drive type of each of the two of the 2*N storage drives based on the voltage received from each of the N analog pins.

A control method for a first device of an inter-integrated circuit (I.sup.2C) system including a microcontroller unit (MCU), includes receiving a first indication from the MCU of the I.sup.2C system, wherein the first indication configures the first device from a slave mode to a master mode; polling the first device itself for status information of the first device when the first device is in the master mode; determining whether the status information of the first device matches a target status after polling; and determining to perform a parameter adjustment on a second device of the I.sup.2C system when determining that the status information of the first device matches the target status.

A control method for a first device of an inter-integrated circuit (I.sup.2C) system including a microcontroller unit (MCU), includes receiving a first indication from the MCU of the I.sup.2C system, wherein the first indication configures the first device from a slave mode to a master mode; polling the first device itself for status information of the first device when the first device is in the master mode; determining whether the status information of the first device matches a target status after polling; and determining to perform a parameter adjustment on a second device of the I.sup.2C system when determining that the status information of the first device matches the target status.

The present invention provides a scheduling method for a peripheral component interconnect express (PCIe) switch of an electronic system. The PCIe switch is utilized for handling input/output requests of a host of the electronic system. The scheduling method includes the PCIe switch determining a scheduling sequence of message signal interrupts (MSIs) and read/write requests corresponding to the input/output requests according to amount of the message signal interrupts corresponding to the input/output requests; and the PCIe switch handling the message signal interrupts and the read/write requests according to the scheduling sequence.

The present invention provides a scheduling method for a peripheral component interconnect express (PCIe) switch of an electronic system. The PCIe switch is utilized for handling input/output requests of a host of the electronic system. The scheduling method includes the PCIe switch determining a scheduling sequence of message signal interrupts (MSIs) and read/write requests corresponding to the input/output requests according to amount of the message signal interrupts corresponding to the input/output requests; and the PCIe switch handling the message signal interrupts and the read/write requests according to the scheduling sequence.

A topology-aware parallel reduction method, system, and recording medium including a partitioning device configured to partition data in each accelerator of a plurality of accelerators into partitions based on a topology of connections between the plurality of accelerators and a control device configured to control, based on a topology of connections between the plurality of accelerators, a type of parallel reduction of data to use.

A topology-aware parallel reduction method, system, and recording medium including a partitioning device configured to partition data in each accelerator of a plurality of accelerators into partitions based on a topology of connections between the plurality of accelerators and a control device configured to control, based on a topology of connections between the plurality of accelerators, a type of parallel reduction of data to use.

A transmission unit for connection to a first bus system, the transmission unit receiving messages via the first bus system, the messages being constructed as a succession of a first bit sequence, of at least one control signal and of a second bit sequence, the first bit sequence of a received message being forwarded by the transmission unit to a processing station, at least one predefined control signal of the received message being checked by the transmission unit, the second bit sequence of the received message being forwarded by the transmission unit to the processing station if the predefined signal of the received message has a predefined value, instead of the second bit sequence, the transmission unit sending a predefined or predefinable terminating bit sequence to the processing station, if the predefined control signal of the received message has a value that deviates from the predefined value.

A transmission unit for connection to a first bus system, the transmission unit receiving messages via the first bus system, the messages being constructed as a succession of a first bit sequence, of at least one control signal and of a second bit sequence, the first bit sequence of a received message being forwarded by the transmission unit to a processing station, at least one predefined control signal of the received message being checked by the transmission unit, the second bit sequence of the received message being forwarded by the transmission unit to the processing station if the predefined signal of the received message has a predefined value, instead of the second bit sequence, the transmission unit sending a predefined or predefinable terminating bit sequence to the processing station, if the predefined control signal of the received message has a value that deviates from the predefined value.

Disclosed are methods and apparatus for multiplex operation of an electronic transmitting apparatus, comprising establishing logical channels between logical data producers and respective logical data consumers, the logical channels operable to pass data over a serial physical channel, constructing by a producer a payload, identifying a respective consumer, arbitrating use of the serial physical channel between logical channels to control sending of payloads, injecting a channel-specific logical protocol stop indicator into a data flow over the serial physical channel to instruct a receiving router to stop receipt of a previously started data flow and route the payload to a consumer, and sending at least a first uninterruptible data unit of the payload over the serial physical channel. Corresponding methods and apparatus are provided to enable a receiver to route payloads to consumers according to received logical protocol stop indicators.