The present invention discloses an interrupt controller, including: a sampling unit adapted to receive interrupts from various interrupt sources coupled to the interrupt controller and perform sampling on the received various interrupts; and a priority arbitration unit adapted to classify the received various interrupts into a plurality of interrupt segments, where each interrupt segment includes one or more sampled interrupts, and determine, segment by segment an interrupt with the highest priority in a selected segment, until an interrupt with the highest priority among all interrupts is identified through arbitration and used as an to-be-responded-to interrupt. The present invention further discloses a processor including the interrupt controller, and a system-on-chip.

In some embodiments, the invention involves using a weighted arbiter switch to provide fairness in passing input streams through a plurality of input ports to an output port. The weighted arbiter switches may be combined in a hierarchical architecture to enable routing through many levels of switches. Each input port has an associated flow counter to count input stream traffic through the input port. An arbiter switch uses the flow counts and weights from arbiter switches at a lower level in the hierarchy to generate a fairly distributed routing of input streams through the output port. Other embodiments are described and claimed.

In some embodiments, the invention involves using a weighted arbiter switch to provide fairness in passing input streams through a plurality of input ports to an output port. The weighted arbiter switches may be combined in a hierarchical architecture to enable routing through many levels of switches. Each input port has an associated flow counter to count input stream traffic through the input port. An arbiter switch uses the flow counts and weights from arbiter switches at a lower level in the hierarchy to generate a fairly distributed routing of input streams through the output port. Other embodiments are described and claimed.

A method for bandwidth allocation includes receiving requests for bus channel access from two or more master devices. Next, the method selects one of priority-based allocation or credit-based allocation. Upon selecting the priority-based allocation, the method grants bus channel access based on pre-assigned priorities for bus channel access. Upon selecting credit-based allocation, the method grants bus channel access based on pre-allocated credits for bus channel access, and the method decrements the credit from the master device that has been granted bus channel access.

A method for bandwidth allocation includes receiving requests for bus channel access from two or more master devices. Next, the method selects one of priority-based allocation or credit-based allocation. Upon selecting the priority-based allocation, the method grants bus channel access based on pre-assigned priorities for bus channel access. Upon selecting credit-based allocation, the method grants bus channel access based on pre-allocated credits for bus channel access, and the method decrements the credit from the master device that has been granted bus channel access.

In one aspect of the present description, in an input/output (I/O) device having multiple CPUs and multiple I/O ports, a cycle of I/O port rotations is initiated in which each port rotation of the cycle includes rotating an assignment of at least one I/O port from one CPU to a different CPU of a plurality of the CPUs. In the illustrated embodiment, an I/O port assignment for each CPU of the plurality CPUs is rotated for at least a portion of the cycle. Other features and aspects may be realized, depending upon the particular application.

In one aspect of the present description, in an input/output (I/O) device having multiple CPUs and multiple I/O ports, a cycle of I/O port rotations is initiated in which each port rotation of the cycle includes rotating an assignment of at least one I/O port from one CPU to a different CPU of a plurality of the CPUs. In the illustrated embodiment, an I/O port assignment for each CPU of the plurality CPUs is rotated for at least a portion of the cycle. Other features and aspects may be realized, depending upon the particular application.

Methods and systems for pre-fetching operations include executing event callbacks in an event loop using a processor until execution stops on a polling request. A path walk is performed on future events in the event loop until the polling request returns to pre-fetch information for the future events into a processor cache associated with the processor. Execution of the event callbacks in the event loop is resumed after the polling request returns.

Methods and systems for pre-fetching operations include executing event callbacks in an event loop using a processor until execution stops on a polling request. A path walk is performed on future events in the event loop until the polling request returns to pre-fetch information for the future events into a processor cache associated with the processor. Execution of the event callbacks in the event loop is resumed after the polling request returns.

A method of implementing a multi-threaded device driver for a computer system is disclosed. A polling device driver is partitioned into a plurality of driver threads for controlling a device of a computer system. The device has a first device state of an unscouted state and a scouted state, and a second device state of an inactive state and an active state. A driver thread of the plurality of driver threads determines that the first device state of the device state is in the unscouted state, and changes the first state of the device to the scouted state. The driver thread further determines that the second device state of the device is in the inactive state and changes the second device state of the device to the active state. The driver thread executes an operation on the device during a pre-determined time slot configured for the driver thread.