G06F13/37

SCALABLE HIGH-SPEED ROUND-ROBIN ARBITER TREE
20220365894 · 2022-11-17 ·

The methods and systems may provide a scalable round-robin arbiter tree that performs round-robin arbitration for a plurality of requests received from a set of requestors. The round-robin arbiter may stack a plurality of round-robin cells in stages where an output of a first stage of round-robin cells is an input to a next stage of round-robin cells. The round-robin arbiter may transform an arbitration state at each stage of the arbitration and propagate the arbitration state into the next stage for arbitration. The arbitration state from the final stage round-robin cell is fed back to the first stage of the round-robin cells and used in a subsequent arbitration round.

MEDICAL DEVICES WITH CIRCUITRY FOR CAPTURING AND PROCESSING PHYSIOLOGICAL SIGNALS
20230049000 · 2023-02-16 ·

A medical device comprises a control system, processing modules, and a wire bundle connecting the control system to the processing modules, the wire bundle comprising control lines and data lines. Each processing module is coupled to a respective set of sensors arranged to interface with a biological tissue site, the sensors being configured to capture analog physiological signals generated from the biological tissue site. The control system is configured to generate a control signal on the control lines to initiate a data collection cycle by the processing modules. In response to the control signal, each processing module is configured to perform a respective data collection process which comprises (i) capturing and processing an analog physiological signal on each enabled sensor to generate a data sample for each analog physiological signal captured on each enabled sensor, and (ii) outputting data samples to the control system on the data lines.

MEDICAL DEVICES WITH CIRCUITRY FOR CAPTURING AND PROCESSING PHYSIOLOGICAL SIGNALS
20230049000 · 2023-02-16 ·

A medical device comprises a control system, processing modules, and a wire bundle connecting the control system to the processing modules, the wire bundle comprising control lines and data lines. Each processing module is coupled to a respective set of sensors arranged to interface with a biological tissue site, the sensors being configured to capture analog physiological signals generated from the biological tissue site. The control system is configured to generate a control signal on the control lines to initiate a data collection cycle by the processing modules. In response to the control signal, each processing module is configured to perform a respective data collection process which comprises (i) capturing and processing an analog physiological signal on each enabled sensor to generate a data sample for each analog physiological signal captured on each enabled sensor, and (ii) outputting data samples to the control system on the data lines.

Systems and methods for fast round robin for wide masters
11500790 · 2022-11-15 · ·

A master request comprising a plurality of bits is received, each bit representing whether a host device of a plurality of host devices has issued a memory access request. The master request is divided into a plurality of slices, each respective slice containing a subset of the plurality of bits corresponding a subset of host devices. Based on the respective subsets of the plurality of bits, it is determined whether each respective slice contains at least one memory access request. A first round robin process then begins in which it is determined whether each respective slice contains a memory access request. If so, any memory access request contained in the respective slice are processed via a second round robin process before proceeding to process memory access requests of another slice. If the respective slice contains no memory access requests, processing skips to a next slice without processing the respective slice.

Systems and methods for fast round robin for wide masters
11500790 · 2022-11-15 · ·

A master request comprising a plurality of bits is received, each bit representing whether a host device of a plurality of host devices has issued a memory access request. The master request is divided into a plurality of slices, each respective slice containing a subset of the plurality of bits corresponding a subset of host devices. Based on the respective subsets of the plurality of bits, it is determined whether each respective slice contains at least one memory access request. A first round robin process then begins in which it is determined whether each respective slice contains a memory access request. If so, any memory access request contained in the respective slice are processed via a second round robin process before proceeding to process memory access requests of another slice. If the respective slice contains no memory access requests, processing skips to a next slice without processing the respective slice.

Scaling performance in a storage server with storage devices

Provided is a method of packet processing, the method including receiving an input/output (IO) request from a host, selecting a drive corresponding to the IO request using a hashing algorithm or a round-robin technique, and establishing a connection between the host and the drive.

Scaling performance in a storage server with storage devices

Provided is a method of packet processing, the method including receiving an input/output (IO) request from a host, selecting a drive corresponding to the IO request using a hashing algorithm or a round-robin technique, and establishing a connection between the host and the drive.

HIERARCHICAL RING-BASED INTERCONNECTION NETWORK FOR SYMMETRIC MULTIPROCESSORS

A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

DYNAMIC ADDRESSING SYSTEM AND METHOD IN A DIGITAL COMMUNICATION INTERFACE
20220327077 · 2022-10-13 · ·

In a digital communication system, a master device and a number of slave devices are coupled in communication with the master device over a shared data communication bus. During an address assignment procedure, the master device assigns different respective dynamic addresses to the slave devices in order to address the slave devices for data communication; during the address assignment procedure, the slave devices are arranged in a daisy-chain configuration, wherein each slave device has a daisy-chain input and a daisy-chain output, the daisy-chain input of a slave device being coupled to the daisy-chain output of a previous slave device in the daisy chain configuration, the daisy-chain input of a first slave device being coupled to a daisy-chain enabling output of the master device; in particular, the master device is configured to assign the respective dynamic addresses to the slave devices based on their arrangement in the daisy-chain configuration.

DYNAMIC ADDRESSING SYSTEM AND METHOD IN A DIGITAL COMMUNICATION INTERFACE
20220327077 · 2022-10-13 · ·

In a digital communication system, a master device and a number of slave devices are coupled in communication with the master device over a shared data communication bus. During an address assignment procedure, the master device assigns different respective dynamic addresses to the slave devices in order to address the slave devices for data communication; during the address assignment procedure, the slave devices are arranged in a daisy-chain configuration, wherein each slave device has a daisy-chain input and a daisy-chain output, the daisy-chain input of a slave device being coupled to the daisy-chain output of a previous slave device in the daisy chain configuration, the daisy-chain input of a first slave device being coupled to a daisy-chain enabling output of the master device; in particular, the master device is configured to assign the respective dynamic addresses to the slave devices based on their arrangement in the daisy-chain configuration.