An apparatus includes an arbiter and a plurality of arithmetic processors, each including an arithmetic circuit and a measuring circuit. The arithmetic circuit executes an arithmetic process, and the measuring circuit measures a progress level indicating a progress of the arithmetic process executed by the arithmetic circuit. Upon receiving access requests to an external device from first arithmetic processors included in the plurality of arithmetic processors, the arbiter arbitrates the access requests, based on a result of comparing the progress levels measured by the measuring circuits of the first arithmetic processors.

Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.

An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.

An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.

An interface module has at least a configuration connection, a reset connection, a transmission connection and a reception connection. The interface module also has at least a first interface processing unit and a second interface processing unit which differs from the first interface processing unit and the connections of which can be connected to the connections of the interface module via a multiplexer. Only one set of interface connections needs to be provided on the interface module. The multiplexer is controlled by a level at the

An interface module has at least a configuration connection, a reset connection, a transmission connection and a reception connection. The interface module also has at least a first interface processing unit and a second interface processing unit which differs from the first interface processing unit and the connections of which can be connected to the connections of the interface module via a multiplexer. Only one set of interface connections needs to be provided on the interface module. The multiplexer is controlled by a level at the

An interrupt handler unit (130) generates a timer interrupt at an interrupt time, and executes an interrupt preparation process. A wait time period measurement unit (142) a measures a time period from completion of the interrupt preparation process to generation of a start request (201) as a wait time period. A time calculation unit (441) calculates a subtraction time period based on the wait time period measured by the wait time period measurement unit (142), and calculates a preparation time period that is the sum of a time period obtained by subtracting the subtraction time period from the wait time period and a processing time period of the interrupt preparation process. The time calculation unit (441) stores a time obtained by shifting back the preparation time period from the time of a next start request (201), as a next interrupt time, in a time storage unit (442).

An interrupt handler unit (130) generates a timer interrupt at an interrupt time, and executes an interrupt preparation process. A wait time period measurement unit (142) a measures a time period from completion of the interrupt preparation process to generation of a start request (201) as a wait time period. A time calculation unit (441) calculates a subtraction time period based on the wait time period measured by the wait time period measurement unit (142), and calculates a preparation time period that is the sum of a time period obtained by subtracting the subtraction time period from the wait time period and a processing time period of the interrupt preparation process. The time calculation unit (441) stores a time obtained by shifting back the preparation time period from the time of a next start request (201), as a next interrupt time, in a time storage unit (442).

The invention pertains to automatically addressing devices on a network. The controller tests each address from a list of available addresses. If the control device receives a response the corresponding address is eliminated from the list of available addresses. The control device sends an arming signal which is received by all participating devices. The devices prepare for a triggering signal. When the trigger signal is received each device waits a random amount of time. During this time each device looks for communication on the bus, if communication is detected the device quits timing and remains unaddressed, if not it sends a signal to the control device to accept the address.

The invention pertains to automatically addressing devices on a network. The controller tests each address from a list of available addresses. If the control device receives a response the corresponding address is eliminated from the list of available addresses. The control device sends an arming signal which is received by all participating devices. The devices prepare for a triggering signal. When the trigger signal is received each device waits a random amount of time. During this time each device looks for communication on the bus, if communication is detected the device quits timing and remains unaddressed, if not it sends a signal to the control device to accept the address.