A processing and storage circuit includes an internal bus, one or more first-level internal memory units, a central processing unit (CPU), one or more hardware acceleration engines, and an arbiter. The first-level internal memory unit is coupled to the internal bus. The CPU includes a second-level internal memory unit, and is configured to access the first-level internal memory unit via the internal bus, and when the CPU accesses data, the first-level internal memory unit is accessed preferentially. The hardware acceleration engine is configured to access the first-level internal memory unit via the internal bus. The arbiter is coupled to the internal bus, configured to decide whether the CPU or the hardware acceleration engine be allowed to access the first-level internal memory unit. The arbiter sets the priority of the CPU accessing the first-level internal memory unit to be over the hardware acceleration engine.

A processing and storage circuit includes an internal bus, one or more first-level internal memory units, a central processing unit (CPU), one or more hardware acceleration engines, and an arbiter. The first-level internal memory unit is coupled to the internal bus. The CPU includes a second-level internal memory unit, and is configured to access the first-level internal memory unit via the internal bus, and when the CPU accesses data, the first-level internal memory unit is accessed preferentially. The hardware acceleration engine is configured to access the first-level internal memory unit via the internal bus. The arbiter is coupled to the internal bus, configured to decide whether the CPU or the hardware acceleration engine be allowed to access the first-level internal memory unit. The arbiter sets the priority of the CPU accessing the first-level internal memory unit to be over the hardware acceleration engine.

A memory access device includes: a data processor configured to output an access request requesting access to a memory connected to a data bus, perform a data processing on data in the accessed memory, and provide notification of a progress status of the data processing; a priority switching control part configured to determine an urgency of the data processing by the data processor according to the progress status of the data processing notified from the data processor, and output a priority switching signal notifying switching of a priority of the data processor; and a bus arbiter connected to the data bus, configured to change the priority of the data processor according to the priority switching signal to arbitrate the access request output from the data processor, and control access to the memory according to the access request that has been arbitrated.

A memory access device includes: a data processor configured to output an access request requesting access to a memory connected to a data bus, perform a data processing on data in the accessed memory, and provide notification of a progress status of the data processing; a priority switching control part configured to determine an urgency of the data processing by the data processor according to the progress status of the data processing notified from the data processor, and output a priority switching signal notifying switching of a priority of the data processor; and a bus arbiter connected to the data bus, configured to change the priority of the data processor according to the priority switching signal to arbitrate the access request output from the data processor, and control access to the memory according to the access request that has been arbitrated.

A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. Secondary devices on the SPI bus can be configured to include or use respective static identifiers that uniquely identify or address each device. In an example, the primary device can communicate messages using the SPI bus, and the messages can include or use a device identification field. In an example, secondary devices on the SPI bus can be configured to monitor the device identification fields of incoming messages. If a message includes an identification field that corresponds to an identifier of a particular device, then the particular device can attend to the message, and other devices without the same identifier can disregard the message.

A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. Secondary devices on the SPI bus can be configured to include or use respective static identifiers that uniquely identify or address each device. In an example, the primary device can communicate messages using the SPI bus, and the messages can include or use a device identification field. In an example, secondary devices on the SPI bus can be configured to monitor the device identification fields of incoming messages. If a message includes an identification field that corresponds to an identifier of a particular device, then the particular device can attend to the message, and other devices without the same identifier can disregard the message.

A bus system for a process system, having a first bus subscriber which transmits bus messages and having at least one first bus subscriber which receives bus messages, wherein the transmitting first bus subscriber and the receiving first bus subscriber are connected to one another via a first data bus, wherein the transmitting first bus subscriber is designed such that it transmits control commands to the receiving first bus subscriber, wherein the receiving first bus subscriber is designed such that it executes the control commands of the transmitting first bus subscriber and achieves the object of providing a bus system that is designed to be fail-safe in a special way.

A bus system for a process system, having a first bus subscriber which transmits bus messages and having at least one first bus subscriber which receives bus messages, wherein the transmitting first bus subscriber and the receiving first bus subscriber are connected to one another via a first data bus, wherein the transmitting first bus subscriber is designed such that it transmits control commands to the receiving first bus subscriber, wherein the receiving first bus subscriber is designed such that it executes the control commands of the transmitting first bus subscriber and achieves the object of providing a bus system that is designed to be fail-safe in a special way.

Systems, apparatuses, methods, and computer-readable media are provided for managing operations associated with multi-device serial read for communication buses. Embodiments include a protocol controller coupled to a transmitter and receiver assembly of a device to control the transmitter and receiver assembly to perform a multi-device read protocol to read from a plurality of devices coupled to the serial bus using a single device group read command. Other embodiments may be described and/or claimed.

Systems, apparatuses, methods, and computer-readable media are provided for managing operations associated with multi-device serial read for communication buses. Embodiments include a protocol controller coupled to a transmitter and receiver assembly of a device to control the transmitter and receiver assembly to perform a multi-device read protocol to read from a plurality of devices coupled to the serial bus using a single device group read command. Other embodiments may be described and/or claimed.